6+ EDA Jobs in India

INNOPHASE is a rapidly growing pre-IPO communications semiconductor company with headquarters in San Diego, CA, and advanced design centers in Irvine, CA, San Jose, CA, Kista, Sweden, and Bangalore, India. We pioneered the industry’s lowest power Wi-Fi radio architecture for IoT applications and a revolutionary 5G platform that will transform cellular network deployments. Utilizing our breakthrough, patented, wireless technology we are bringing to market a portfolio of SoCs and modules with a unique value proposition for IoT and 5G applications.

InnoPhase Bangalore is looking for a Senior Engineer, Digital Physical Design to join a growing start

up semiconductor development organization and to help drive excellence in our IoT products.

Roles & Responsibilities

Design, Develop and execute physical design implementation of low-power and high-performance SoC, including

logic synthesis, floorplan and power plan, power domain specification, place and route, clock tree synthesis, static

timing analysis, IR drop analysis, EM, and physical verification in advanced technology nodes.

• Work with the RTL and System design teams to drive the physical design of the device in the early design cycle.
• Design, implement and verify suitable methodology that meets the QoR goals.
• Resolve design and flow issues related to the physical design, identify potential solutions, and drive

execution.

• Deliver physical design of entire SoC, complete with specification, flow and automation.
• Interface with the RTL design team to drive design modifications to resolve physical design issues and

implement ECOs.

• Use EDA tool-based programming and scripting techniques to automate and improve throughput and quality.
• Interact with tool vendors to drive tool fixes and flow improvements. Perform tool evaluations of new

vendor tools and functions.

Desired Qualities

• Bachelor’s degree (Master’s preferred) in Electrical Engineering or comparable engineering discipline.
• 5 to 8 years of relevant experience is required.
• Experience in physical design and timing closure for advanced nodes.
• Experience in Cadence EDA tools for physical design and verification.
• Experience in floor planning, power planning, CTS specification, place & route, and timing closure.
• Experience in UPF specs design and implementation.
• Be able to work with cross-functional teams, IP, and EDA vendors

INNOPHASE is a rapidly growing communications semiconductor startup with headquarters located in San Diego, CA. It is an exciting time to join InnoPhase and work with a brilliant team of engineers to design innovative wireless products and solutions for IoT/5G.

 

InnoPhase Bangalore is looking for a Senior Design Verification (DV) Engineer to join a growing start up semiconductor development organization and to help drive excellence in our IOT/5G products.

 

Responsibilities:

 

• Follow and help define the team's design verification methodology.
• Write bus functional models that drive and monitor stimulus.
• Plans and implements block and integration level scoreboards and checkers to verify functional behavior.
• Experience constructing chip-level System Verilog and UVM test bench environments, writing System Verilog Assertions (SVAs), with embedded software design and test.
• Develop RAL test plan at SOC/IP level and its implementation.
• Write and analyze functional coverage, providing input to block-level milestones.
• Triage regression failures and identify logic bugs, while driving bug closure.
• Debug test cases and report verification results to achieve the expected code/functional coverage goal. Utilize constrained random verification, functional coverage, code coverage and assertions to achieve goals.

 

Knowledge and Skills Required:

 

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science or equivalent.
• 5+ years of experience in VLSI design or verification
• Excellent collaboration, teamwork and communication skills
• Significant experience in reviewing and modifying IP block verification plans, a real plus if created such plans in collaboration with design engineering.
• Track record of completing IP block verification to acceptable coverage metrics.
• Excellent debugging skills, with experience debugging RTL in the block and/or chip-level environments.
• Working knowledge of OVM or UVM methodologies.
• Good analytical and problem-solving skills.
• Proficient knowledge of programming and scripting, hardware description language, electronic design automation (EDA), and/or FPGA tools.

DATA SCIENTIST-MACHINE LEARNING                           

GormalOne LLP. Mumbai IN

 

Job Description

GormalOne is a social impact Agri tech enterprise focused on farmer-centric projects. Our vision is to make farming highly profitable for the smallest farmer, thereby ensuring India's “Nutrition security”. Our mission is driven by the use of advanced technology. Our technology will be highly user-friendly, for the majority of farmers, who are digitally naive. We are looking for people, who are keen to use their skills to transform farmers' lives. You will join a highly energized and competent team that is working on advanced global technologies such as OCR, facial recognition, and AI-led disease prediction amongst others.

 

GormalOne is looking for a machine learning engineer to join. This collaborative yet dynamic, role is suited for candidates who enjoy the challenge of building, testing, and deploying end-to-end ML pipelines and incorporating ML Ops best practices across different technology stacks supporting a variety of use cases. We seek candidates who are curious not only about furthering their own knowledge of ML Ops best practices through hands-on experience but can simultaneously help uplift the knowledge of their colleagues.

 

Location: Bangalore

 

Roles & Responsibilities

• Individual contributor
• Developing and maintaining an end-to-end data science project
• Deploying scalable applications on different platform
• Ability to analyze and enhance the efficiency of existing products

 

What are we looking for?

• 3 to 5 Years of experience as a Data Scientist
• Skilled in Data Analysis, EDA, Model Building, and Analysis.
• Basic coding skills in Python
• Decent knowledge of Statistics
• Creating pipelines for ETL and ML models.
• Experience in the operationalization of ML models
• Good exposure to Deep Learning, ANN, DNN, CNN, RNN, and LSTM.
• Hands-on experience in Keras, PyTorch or Tensorflow

 

 

Basic Qualifications

• Tech/BE in Computer Science or Information Technology
• Certification in AI, ML, or Data Science is preferred.
• Master/Ph.D. in a relevant field is preferred.

 

 

Preferred Requirements

• Exp in tools and packages like Tensorflow, MLFlow, Airflow
• Exp in object detection techniques like YOLO
• Exposure to cloud technologies
• Operationalization of ML models
• Good understanding and exposure to MLOps

 

 

Kindly note: Salary shall be commensurate with qualifications and experience

 

 

 

 

1.Strong background of ASIC Physical Design: Floor planning, P&R, Extraction, IR Drop Analysis, Static Timing and Signal Integrity.                          
2.Hands-on experience on technology nodes like 7nm, 14nm, 10nm.
3.Good knowledge of EDA tools from Synopsys , Cadence and Mentor              
4.Hands-on experience in floor planning, placement optimizations, CTS and routing.                                  
5.Hands-on experience in cadence or Synopsys tool (Encounter, ICC, PT/PTSI, TEMPUS, DC, RC, VOLTAS)

Your challenge
The mission of R&D IT Design Infrastructure is to offer a state-of-the-art design environment
for the chip hardware designers. The R&D IT design environment is a complex landscape of EDA Applications, High Performance Compute, and Storage environments - consolidated in five regional datacenters. Over 7,000 chip hardware designers, spread across 40+ locations around the world, use this state-of-the-art design environment to design new chips and drive the innovation of company. The following figures give an idea about the scale: the landscape has more 75,000+ cores, 30+ PBytes of data, and serves 2,000+ CAD applications and versions. The operational service teams are globally organized to cover 24/7 support to the chip hardware design and software design projects.
Since the landscape is really too complex to manage the traditional way, it is our strategy to transform our R&D IT design infrastructure into “software-defined datacenters”. This transformation entails a different way of work and a different mind-set (DevOps, Site Reliability Engineering) to ensure that our IT services are reliable. That’s why we are looking for a DevOps Linux Engineer to strengthen the team that is building a new on-premise software defined virtualization and containerization platform (PaaS) for our IT landscape, so that we can manage it with best practices from software engineering and offer the IT service reliability which is required by our chip hardware design community.
It will be your role to develop and maintain the base Linux OS images that are offered via automation to the customers of the internal (on-premise) cloud platforms.

Your responsibilities as DevOps Linux Engineer:
• Develop and maintain the base RedHat Linux operating system images
• Develop and maintain code to configure and test the base OS image
• Provide input to support the team to design, develop and maintain automation
products with playbooks (YAML) and modules (Python/PowerShell) in tools like
Ansible Tower and Service-Now
• Test and verify the code produced by the team (including your own) to continuously
improve and refactor
• Troubleshoot and solve incidents on the RedHat Linux operating system
• Work actively with other teams to align on the architecture of the PaaS solution
• Keep the Base OS image up2date via patches or make sure patches are available to
the virtual machine owners
• Train team members and others with your extensive automation knowledge
• Work together with ServiceNow developers in your team to provide the best intuitive
end-user experience possible for the virtual machine OS deployments

We are looking for a DevOps engineer/consultant with the following characteristics:
• Master or Bachelor degree
• You are a technical, creative, analytical and open-minded engineer that is eager to
learn and not afraid to take initiative.
• Your favorite t-shirt has “Linux” or “RedHat” printed on it at least once.
• Linux guru: You have great knowledge Linux servers (RedHat), RedHat Satellite 6
and other RedHat products
• Experience in Infrastructure services, e.g., Networking, DNS, LDAP, SMTP
• DevOps mindset: You are a team-player that is eager to develop and maintain cool
products to automate/optimize processes in a complex IT infrastructure and are able
to build and maintain productive working relationships
• You have great English communication skills, both verbally as in writing.
• No issue to work outside business hours to support the platform for critical R&D
Applications

Other competences we value, but are not strictly mandatory:
• Experience with agile development methods, like Scrum, and are convinced of its
power to deliver products with immense (business) value.
• “Security” is your middle name, and you are always challenging yourself and your
colleagues to design and develop new solutions as security tight as possible.
• Being a master in automation and orchestration with tools like Ansible Tower (or
comparable) and feel comfortable with developing new modules in Python or
PowerShell.
• It would be awesome if you are already a true Yoda when it comes to code version
control and branching strategies with Git, and preferably have worked with GitLab
before.
• Experience with automated testing in a CI/CD pipeline with Ansible, Python and tools
like Selenium.
• An enthusiast on cloud platforms like Azure & AWS.
• Background in and affinity with R&D

Overview The Staff Software Engineer – EDA is key member of the QuickLogic India team and will report to Director of Software of QuickLogic India (QLI). The Staff Software Engineer EDA will be an integral part of EDA tools team at QLI, with primary responsibility for full life cycle development of EDA tools for programmable fabric devices. The role holder will be also responsible for identifying and resolving problems based on broad objectives and customer issues. Key responsibilities include but are not limited to: • Full lifecycle software development including design, development, testing and documentation of EDA tools for programmable devices • Utilize Object-oriented programming methodology using C++ & STL for design and implementation of current and next generation QuickLogic products • Perform detailed analysis, identify root causes and arrive at suitable solutions during all phases of the software development lifecycle • Engage and team up with colleagues globally, and leverage technical skills to produce results with a high degree of responsiveness, regardless of time and geographical differences • Resolve wide range of issues in a creative way, exercise judgment in selecting methods and techniques to arrive at solutions Key Activities for the position include but are not limited to: • Immediate work involves development in STA component of Aurora, EDA Software tool. • Take technical ownership of area(s) in EDA flow. It includes proposing, defining & developing new features in ownership area(s); resolving customer issues; mentoring & working in team. • Work on different phases of software development cycle, from gathering requirement specification to delivery. • Design & develop the assigned projects, following best practices in defining object-oriented methodology and implementing it by effectively using C++ & STL. • Giving utmost importance to quality and robustness of the deliverables. It is achieved by doing a thorough functional unit testing of the implemented features. Education/Knowledge & Skills Profile: • BE/BTech/ME/MTech in CS/Electronics/Electrical Engineering, from Tier-I engineering colleges (IITs, BITS-Pilani, NITs), with 5-9 years of experience in EDA tools development. • Strong academic background and good understanding of data structures and algorithms. • Prior experience in developing projects related to timing either in FPGA specific EDA tool suite or in ASIC specific EDA tool suite. • Strong in object-oriented programming using C++ & STL. • Good Understanding of C, Shell scripting, Makefiles, Tcl & Lex/Yacc • Prior Experience in using SVN/Bug tracking tools • Self-motivated with the ability to work with minimal supervision • Ability to work well in a team • Ability to work well in a dynamic environment and be able to respond positively to change • Superior verbal and written communication skills, in English Behavioral Skills Profile • Results Orientation - Knowing what results are important, and focusing resources to achieve them • Personal Accountability - The willingness to claim ownership for the results provided as a consequence of your involvement, both individually and collectively with others • Team Work – Working effectively and productively with others • Problem solving - The ability to discover, analyze and resolve problems and find solutions to specific issues • Continuous Learning – Taking initiative in learning and implementing new concepts • Flexibility – Agility in Adapting to change • Resiliency – The ability to quickly recover from Adversity • Futuristic Thinking – Imagining, envisioning, projecting and /or predicting what had not yet been realized