Innophase

INNOPHASE is a rapidly growing pre-IPO communications semiconductor company with headquarters in San Diego, CA, and advanced design centers in Irvine, CA, San Jose, CA, Kista, Sweden, and Bangalore, India. We pioneered the industry’s lowest power Wi-Fi radio architecture for IoT applications and a revolutionary 5G platform that will transform cellular network deployments. Utilizing our breakthrough, patented, wireless technology we are bringing to market a portfolio of SoCs and modules with a unique value proposition for IoT and 5G applications.

InnoPhase Bangalore is looking for a Senior Engineer, Digital Physical Design to join a growing start

up semiconductor development organization and to help drive excellence in our IoT products.

Roles & Responsibilities

Design, Develop and execute physical design implementation of low-power and high-performance SoC, including

logic synthesis, floorplan and power plan, power domain specification, place and route, clock tree synthesis, static

timing analysis, IR drop analysis, EM, and physical verification in advanced technology nodes.

• Work with the RTL and System design teams to drive the physical design of the device in the early design cycle.
• Design, implement and verify suitable methodology that meets the QoR goals.
• Resolve design and flow issues related to the physical design, identify potential solutions, and drive

execution.

• Deliver physical design of entire SoC, complete with specification, flow and automation.
• Interface with the RTL design team to drive design modifications to resolve physical design issues and

implement ECOs.

• Use EDA tool-based programming and scripting techniques to automate and improve throughput and quality.
• Interact with tool vendors to drive tool fixes and flow improvements. Perform tool evaluations of new

vendor tools and functions.

Desired Qualities

• Bachelor’s degree (Master’s preferred) in Electrical Engineering or comparable engineering discipline.
• 5 to 8 years of relevant experience is required.
• Experience in physical design and timing closure for advanced nodes.
• Experience in Cadence EDA tools for physical design and verification.
• Experience in floor planning, power planning, CTS specification, place & route, and timing closure.
• Experience in UPF specs design and implementation.
• Be able to work with cross-functional teams, IP, and EDA vendors

INNOPHASE is a rapidly growing communications semiconductor startup with headquarters located in San Diego, CA. It is an exciting time to join InnoPhase and work with a brilliant team of engineers to design innovative wireless products and solutions for IoT/5G.

 

InnoPhase Bangalore is looking for a Senior Design Verification (DV) Engineer to join a growing start up semiconductor development organization and to help drive excellence in our IOT/5G products.

 

Responsibilities:

 

• Follow and help define the team's design verification methodology.
• Write bus functional models that drive and monitor stimulus.
• Plans and implements block and integration level scoreboards and checkers to verify functional behavior.
• Experience constructing chip-level System Verilog and UVM test bench environments, writing System Verilog Assertions (SVAs), with embedded software design and test.
• Develop RAL test plan at SOC/IP level and its implementation.
• Write and analyze functional coverage, providing input to block-level milestones.
• Triage regression failures and identify logic bugs, while driving bug closure.
• Debug test cases and report verification results to achieve the expected code/functional coverage goal. Utilize constrained random verification, functional coverage, code coverage and assertions to achieve goals.

 

Knowledge and Skills Required:

 

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science or equivalent.
• 5+ years of experience in VLSI design or verification
• Excellent collaboration, teamwork and communication skills
• Significant experience in reviewing and modifying IP block verification plans, a real plus if created such plans in collaboration with design engineering.
• Track record of completing IP block verification to acceptable coverage metrics.
• Excellent debugging skills, with experience debugging RTL in the block and/or chip-level environments.
• Working knowledge of OVM or UVM methodologies.
• Good analytical and problem-solving skills.
• Proficient knowledge of programming and scripting, hardware description language, electronic design automation (EDA), and/or FPGA tools.