Senior Physical Design Engineer at Innophase · Bengaluru (Bangalore) · 5 - 10 years · ₹10L - ₹40L / yr · Profitable · Posted 19 Oct 2022
InnoPhase Bangalore is looking for a Senior Engineer, Digital Physical Design to join a growing start
up semiconductor development organization and to help drive excellence in our IoT products.
Roles & Responsibilities
Design, Develop and execute physical design implementation of low-power and high-performance SoC, including
logic synthesis, floorplan and power plan, power domain specification, place and route, clock tree synthesis, static
timing analysis, IR drop analysis, EM, and physical verification in advanced technology nodes.
- Work with the RTL and System design teams to drive the physical design of the device in the early design cycle.
- Design, implement and verify suitable methodology that meets the QoR goals.
- Resolve design and flow issues related to the physical design, identify potential solutions, and drive
- Deliver physical design of entire SoC, complete with specification, flow and automation.
- Interface with the RTL design team to drive design modifications to resolve physical design issues and
- Use EDA tool-based programming and scripting techniques to automate and improve throughput and quality.
- Interact with tool vendors to drive tool fixes and flow improvements. Perform tool evaluations of new
Desired Qualities
- Bachelor’s degree (Master’s preferred) in Electrical Engineering or comparable engineering discipline.
- 5 to 8 years of relevant experience is required.
- Experience in physical design and timing closure for advanced nodes.
- Experience in Cadence EDA tools for physical design and verification.
- Experience in floor planning, power planning, CTS specification, place & route, and timing closure.
- Experience in UPF specs design and implementation.
- Be able to work with cross-functional teams, IP, and EDA vendors
Shubham Vishwakarma
Full Stack Developer - Averlon
About Innophase
About
InnoPhase is a fabless wireless semiconductor platform company specializing in extreme low power wireless radio solutions. It invented the groundbreaking PolaRFusionTM digital radio architecture, a patented semiconductor that dramatically increases battery lifetime 50%+ in typical applications.
Headquarters is located in San Diego, CA with an additional advanced design centers located in Kista Sweden, and Bangalore, India.
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Do you want to own the PMIC, PLL, and PCIe buffer architectures that ship in millions of vehicles? Do you want to build and lead the team solving India's toughest automotive power and clocking challenges?
Role: Head of Engineering
Level Five Cartronics | Fabless Automotive Semiconductor Design
Location: MG Road, Bengaluru, Karnataka, India (On-site)
About Us
Founded by serial Entrepreneurs, Level Five Cartronics is a fabless semiconductor design company headquartered in Bengaluru, building automotive-grade Power Management ICs (PMICs), high-precision oscillators, and high-performance phase-locked loops (PLLs) for the next generation of vehicle electronics. Our portfolio centres on low-EMI power delivery — including spread-spectrum EMI suppression — and low-jitter clocking and interface solutions for safety-critical solutions and infotainment systems. We design DC-DC converters, LDOs, and clock distribution networks (including low-jitter PCIe Gen 4, 5, and 6 buffers) in CMOS and BCD high-voltage processes across the 55nm, 90nm and 180nm nodes. We own our products end to end, from architecture through silicon characterization and productization, as part of India's growing fabless semiconductor ecosystem.
The Role
We are looking for a hands-on Head of Engineering, based at our Bengaluru headquarters, to lead our analog/mixed-signal design organization. This is a senior leadership position for an engineer who has personally taken complex automotive power, clocking, and high-speed interface products from concept to high-volume production — and who can build, mentor, and scale the cross-functional team that does it again and again.
You will set the technical direction for our PMIC, oscillator, PLL, and PCIe buffer roadmaps, own design quality and tape-out readiness, and partner closely with characterization, product, and test engineering to ensure every product meets stringent automotive reliability, jitter, and EMC requirements.
What You'll Do
1. Lead and grow the analog/mixed-signal design, layout, and verification teams across multiple product lines, based out of our Bengaluru engineering center.
2. Own the technical architecture and execution of automotive-grade PMICs, DC-DC converters, LDOs, low phase noise Fractional-N phase-locked loops (PLLs), and low-jitter PCIe Gen 4, 5, and 6 buffers.
3. Target high-speed interface applications by driving low phase noise PLL architectures explicitly optimized for PCIe Gen 4, 5, and 6 standards.
4. Drive designs across CMOS and BCD high-voltage processes at 55nm, 90nm and 180nm, from specification through tape-out and qualification.
5. Set and enforce design methodology, review gates, and tape-out criteria; review schematics, layout, and verification plans personally where it matters.
6. Partner with characterization engineers on lab bring-up, silicon debug, and correlation of measured results to simulation.
7. Work side by side with product engineers on productization, test development, yield, and sustaining.
8. Build and lead cross-functional teams; recruit, develop, and retain top analog and layout talent in India's semiconductor talent market.
9. Be a technical authority and final escalation point for difficult design and silicon issues.
What You'll Bring
- Minimum of 12 years (preferably more) of experience in analog/mixed-signal design, layout, and productization.
- Demonstrated track record of taped-out databases and shipping full products in volume, not just isolated blocks.
- Deep expertise across the full flow: schematic design, layout, and lab characterization (understanding how each one constrains the others).
- Hands-on design of DC-DC converters and LDOs in CMOS and BCD high-voltage processes.
- Expertise in clocking and interfaces: deep understanding of low phase noise design, Fractional-N PLL architectures, and low-jitter PCIe Gen 4, 5, and 6 clock buffers/drivers.
- Experience with PMICs, oscillators, and spread-spectrum / EMI suppression techniques.
- Strong working knowledge of the 55nm, 90nm and 180nm process nodes.
- Extensive experience with Cadence EDA tools across the design and verification flow.
- Mixed-signal behavioral modeling in Verilog (Verilog/Verilog-AMS).
- Proven history of working closely with characterization and product engineers through bring-up and ramp.
- Demonstrated success building, leading, and recruiting cross-functional engineering teams.
Nice to Have
- Automotive qualification experience (AEC-Q100, ISO 26262 / functional safety awareness).
- Strong EMC/EMI design and measurement background.
- Experience scaling an engineering organization in a fabless environment, ideally within India's semiconductor ecosystem.
Why Level Five Cartronics
You'll own real products in a fast-moving automotive market, work across the full design-to-silicon flow, and shape the engineering culture of a growing fabless company based in Bengaluru — one of India's leading semiconductor design hubs. If you've built power, clocking, and high-speed interface products that ship in cars and you want to lead the team that builds the next ones, we'd like to talk.
Level Five Cartronics is an equal opportunity employer.
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Full Stack Developer - Averlon