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SERDES Jobs in Delhi, NCR and Gurgaon

2+ SERDES Jobs in Delhi, NCR and Gurgaon | SERDES Job openings in Delhi, NCR and Gurgaon

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Smart Soc Solutions

at Smart Soc Solutions

6 recruiters
Sayantika Majumdar
Posted by Sayantika Majumdar
Bengaluru (Bangalore), Hyderabad, Noida, Chennai, Kolkata
3 - 20 yrs
₹10L - ₹50L / yr
Analog And Digital Circuits
SERDES
Circuit Design
Very Large Scale Integration (VLSI)
Hardware
+2 more

alog Circuit Design::

  • The candidate should have B.Tech or M.Tech in Electronics/Electrical/VLSI Design Engineering
  • The candidate should have relevant work experience of 7-16 years in Analog and SERDES IO IP design e.g. GPIOs, Thermal Sensor, PLL, ADC/DAC/ Voltage regulators/LDOs, AIB, HBMIO, DDR, HDMI/DP IO, MIPI IO etc.
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Noida
7 - 15 yrs
₹10L - ₹20L / yr
Hardware
PCB
DFM
SPC
SMT
+3 more
Detailed Job Description :-
 Responsible for end to end mapping and quality control of the projects
 Responsible for Design evaluation of mobile phones from standpoint of hardware, schematic and PCB
layout.
 Responsible for database management program for design evaluation from standpoint of HW and MD
design review
 Ensure device quality and manufacturability are built into the development process to ensure good
process robustness from launch by incorporating DFMEA & DFM.
 Conduct internal & external benchmarking of products and implementing QCD ideas.
 Analysis of warranty failures on both process & design level by using SPC & Design guidelines (DFMEA
& DFM) and categorized into SMT process & design failures.
 Project execution from KICK OFF phase to Mass Production by evaluating DFMEA, parts quality &
process validation.
 Develop & execute test plans that address voice of customer (VOC) such as Reliability, Regression &
Functional testing for HW(PCB validation) & Mechanical at both part & product level.
 Estimation of project pricing by bifurcation of key parts PCBA, HW components and mechanical
structure
 Draft documents for process flow, design evaluation - DFMEA, TTM
 Performance evaluation of DUT by Life cycle test, Temperature & humidity mapping, , short circuit
test, breakdown test, cell balancing, BMS parameter verification, self-discharge test, data sheet
verification.
 Validation of HW key parts as Chipset (SoC), DRAM, LCD, TP and Speaker.
 Responsible for planning of complete hardware and reliability testing of handset i.e. current
consumption, basic functioning and battery charging.
 Responsible for benchmark hardware testing and comparison with DUT.
 Responsible for debugging, simulation, and analyzing hardware quality issues.
 Understanding of HW architecture, PCB schematic and layout.
 Review hardware stack for process feasibility and market failure.
 Performing risk assessment to cover all lesson learnt of market issues.
 Understanding of RF instrument functioning & testing of hardware for calls functioning.
 Create detailed, comprehensive and well-structured test plans and test cases.
 Estimate, prioritized, plan and coordinate testing activities.
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