2+ Application Specific Integrated Circuit (ASIC) Jobs in Delhi, NCR and Gurgaon | Application Specific Integrated Circuit (ASIC) Job openings in Delhi, NCR and Gurgaon

AI Engineering Data Specialist – CAD / EDA / Semiconductor Workflows

Full-time | On-site | Gurgaon, Noida, Bangalore | 5+ Years’

Experience

About SoftAge

SoftAge partners with AI research labs and product teams to build and train autonomous agents and foundation models across desktop, web, and engineering platforms. We convert real engineering workflows into structured training data used for next-generation AI systems.

We are looking for experienced engineers from mechanical, electromechanical, electronics, semiconductor, and EDA domains who want to contribute their domain expertise to AI development.

Role Overview

We are hiring engineers with experience in:

• Mechanical Design
• Industrial Design
• Electromechanical Systems
• PCB Design
• EDA and Semiconductor Workflows
• ASIC, FPGA, VLSI, Verification and Physical Design

The role involves performing engineering tasks, documenting workflows, reviewing AI-generated outputs, and helping create datasets and benchmarks for AI systems.

Key Responsibilities

• Execute engineering tasks using industry-standard CAD and EDA tools.
• Create and refine mechanical designs, assemblies, PCB layouts, and semiconductor workflows.
• Break down complex engineering tasks into structured workflows for AI training.
• Record design decisions, actions, and reasoning.
• Review AI-generated outputs and identify errors or failure cases.
• Build and validate datasets and benchmarks used in AI systems.
• Provide technical feedback and maintain process quality.

Required Qualifications

• B.Tech, M.Tech, or PhD in Mechanical Engineering, Industrial Design, Electrical Engineering, Electronics Engineering, VLSI, Microelectronics, or related disciplines.
• 5+ years of relevant industry experience.
• Strong technical documentation and problem-solving skills.
• Hands-on experience with one or more of the following tools:

CAD and Mechanical Design Tools

• SolidWorks
• Fusion 360
• CATIA
• Creo

PCB and Electronics Tools

• KiCad
• Altium
• Eagle

Semiconductor and EDA Tools

• Cadence
• Synopsys
• Siemens EDA
• Ansys
• Similar industry tools

Preferred Qualifications

• Experience with PCB-integrated enclosure design and electromechanical assemblies.
• Familiarity with DFM, thermal management, grounding, and mechanical-electrical integration.
• Experience in ASIC, FPGA, RTL, STA, DFT, UVM, Physical Design, Analog or Mixed-Signal flows.
• Python or scripting experience.
• Exposure to automation workflows.
• Familiarity with AI-assisted engineering tools or LLM-based systems.
• Previous experience in AI data creation or annotation.

Ideal Candidates

Engineers from:

• Semiconductor companies
• Product engineering teams
• Research labs
• High-growth start-ups

Individuals who combine strong technical expertise with structured reasoning and documentation skills.

Why Join SoftAge

• Work on AI systems used in engineering and design software.
• Contribute to the next generation of AI-powered engineering tools.
• Collaborate with AI researchers and engineering teams.
• Apply years of domain expertise to real-world AI development.

Selected candidates will be required to sign confidentiality and invention assignment agreements. Work quality and process adherence will be audited.

How to Apply

Interested candidates can apply using the form below:

Mandatory: 👉 https://forms.gle/pr77H91zVzNRWntu5

Dear Connections,

Roles & Responsibility:-
Should execute block level floor planning, PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks.

Physical Design Implementation on advanced technology nodes like 28nm, 20nm for block level implementation. Good understanding on low power concepts. Good understanding on top level physical design, partitioning and timing constraints, IR Drop.

Candidate should be from semiconductor/'ASIC industry
Excellent knowledge on GDS To Netlift