Dear Connections,
Roles & Responsibility:-
Should execute block level floor planning, PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks.
Physical Design Implementation on advanced technology nodes like 28nm, 20nm for block level implementation. Good understanding on low power concepts. Good understanding on top level physical design, partitioning and timing constraints, IR Drop.
Candidate should be from semiconductor/'ASIC industry
Excellent knowledge on GDS To Netlift
Shubham Vishwakarma
Full Stack Developer - Averlon
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Full Stack Developer - Averlon