5+ Application Specific Integrated Circuit (ASIC) Jobs in Bangalore (Bengaluru) | Application Specific Integrated Circuit (ASIC) Job openings in Bangalore (Bengaluru)

MANDATORY CRITERIA:

• Education: B.Tech / M.Tech in ECE / CSE / IT
• Experience: 10–12 years in hardware board design, system hardware engineering, and full product deployment cycles
• Proven expertise in digital, analog, and power electronic circuit analysis & design
• Strong hands-on experience designing boards with SoCs, FPGAs, CPLDs, and MPSoC architectures
• Deep understanding of signal integrity, EMI/EMC, and high-speed design considerations
• Must have successfully completed at least two hardware product development cycles from high-level design to final deployment
• Ability to independently handle schematic design, design analysis (DC drop, SI), and cross-team design reviews
• Experience in sourcing & procurement of electronic components, PCBs, and mechanical parts for embedded/IoT/industrial hardware
• Strong experience in board bring-up, debugging, issue investigation, and cross-functional triage with firmware/software teams
• Expertise in hardware validation, test planning, test execution, equipment selection, debugging, and report preparation
• Proficiency in Cadence Allegro or Altium EDA tools (mandatory)
• Experience coordinating with layout, mechanical, SI, EMC, manufacturing, and supply chain teams
• Strong understanding of manufacturing services, production pricing models, supply chain, and logistics for electronics/electromechanical components

DESCRIPTION:

COMPANY OVERVIEW:

The company is a semiconductor and embedded system design company with a focus on Embedded, Turnkey ASICs, Mixed Signal IP, Semiconductor & Product Engineering and IoT solutions catering to Aerospace & Defence, Consumer Electronics, Automotive, Medical and Networking & Telecommunications.

REQUIRED SKILLS:

• Extensive experience in hardware board designs and towards multiple product field deployment cycles.
• Strong foundation and expertise in analyzing digital, Analog and power electronic circuits.
• Proficient with SoC, FPGAs, CPLD and MPSOC architecture-based board designs.
• Knowledgeable in signal integrity, EMI/EMC concepts for digital and power electronics.
• Completed at least two project from high-level design to final product level deployment.
• Capable of independently managing product’s schematic, design analysis DC Drop, Signal Integrity, and coordinating reviews with peer of layout, mechanical, SI, and EMC teams.
• Sourcing and procurement of electronic components, PCBs, and mechanical parts for cutting-edge IoT, embedded, and industrial product development.
• Experienced in board bring-up, issue investigation, and triage in collaboration with firmware and software teams.
• Skilled in preparing hardware design documentation, validation test planning, identifying necessary test equipment, test development, execution, debugging, and report preparation.
• Effective communication and interpersonal skills for collaborative work with cross-functional teams, including post-silicon bench validation, BIOS, and driver development/QA.
• Hands-on experience with Cadence Allegro/Altium EDA tools is essential.
• Familiarity with programming and scripting languages like Python and Perl, and experience in test automation is advantageous.
• Should have excellent exposure with coordination of Manufacturing Services, pricing model for production value supply chain & Logistics in electronics and electromechanical components domain.

Physical Design - JD

Experience: 2-20 yrs
1.Strong background of ASIC Physical Design: Floor planning, P&R, Extraction, IR Drop Analysis, Static Timing and Signal Integrity.                          
2.Hands-on experience on technology nodes like 7nm, 14nm, 10nm.
3.Good knowledge of EDA tools from Synopsys , Cadence and Mentor              
4.Hands-on experience in floor planning, placement optimizations, CTS and routing.                                  
5.Hands-on experience in cadence or Synopsys tool (Encounter, ICC, PT/PTSI, TEMPUS, DC, RC, VOLTAS)

Dear Connections,

Roles & Responsibility:-
Should execute block level floor planning, PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks.

Physical Design Implementation on advanced technology nodes like 28nm, 20nm for block level implementation. Good understanding on low power concepts. Good understanding on top level physical design, partitioning and timing constraints, IR Drop.

Candidate should be from semiconductor/'ASIC industry
Excellent knowledge on GDS To Netlift