4+ Very Large Scale Integration (VLSI) Jobs in Bangalore (Bengaluru) | Very Large Scale Integration (VLSI) Job openings in Bangalore (Bengaluru)

INNOPHASE is a rapidly growing communications semiconductor startup with headquarters located in San Diego, CA. It is an exciting time to join InnoPhase and work with a brilliant team of engineers to design innovative wireless products and solutions for IoT/5G.

InnoPhase Bangalore is looking for a Senior Design Verification (DV) Engineer to join a growing start up semiconductor development organization and to help drive excellence in our IOT/5G products.

Responsibilities:

• Follow and help define the team's design verification methodology.
• Write bus functional models that drive and monitor stimulus.
• Plans and implements block and integration level scoreboards and checkers to verify functional behavior.
• Experience constructing chip-level System Verilog and UVM test bench environments, writing System Verilog Assertions (SVAs), with embedded software design and test.
• Develop RAL test plan at SOC/IP level and its implementation.
• Write and analyze functional coverage, providing input to block-level milestones.
• Triage regression failures and identify logic bugs, while driving bug closure.
• Debug test cases and report verification results to achieve the expected code/functional coverage goal. Utilize constrained random verification, functional coverage, code coverage and assertions to achieve goals.

Knowledge and Skills Required:

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science or equivalent.
• 5+ years of experience in VLSI design or verification
• Excellent collaboration, teamwork and communication skills
• Significant experience in reviewing and modifying IP block verification plans, a real plus if created such plans in collaboration with design engineering.
• Track record of completing IP block verification to acceptable coverage metrics.
• Excellent debugging skills, with experience debugging RTL in the block and/or chip-level environments.
• Working knowledge of OVM or UVM methodologies.
• Good analytical and problem-solving skills.
• Proficient knowledge of programming and scripting, hardware description language, electronic design automation (EDA), and/or FPGA tools.

Custom Memory Design

 SRAM/custom circuit design and standard cell design 

Job description

Rivos Custom Circuits team is seeking highly motivated candidates to develop state of the art custom SRAM memories, Register file memories, memory compilers and standard cells to improve circuit performance, optimize dynamic and static power and support silicon bring up. The role will be at the center of a state-of-the-art circuit design effort, interfacing with all disciplines and have a critical impact on getting products to market quickly.

Responsibilities

• Responsible for designing and delivering custom circuits from scratch.
• Drive design and development of SRAM, register file, custom cells to enable high performance and low power designsWork with microarchitecture team to gather specifications
• Drive optimal implementation Conduct early sizing estimates and PPA analysis. Perform design entry and simulations for optimal design sizingWork closely with mask designers on custom design implementation, DFM and yield enhancement featuresCollaborate with the CPU and SoC Physical design teams on floorplanning, placement, timing and power closure of the custom designInteract with technology team
• Participate in developing design and test plans Collaborate with the CAD team and drive design flow enhancements

Qualification

• Candidates must have 7+ years of experience in transistor level custom circuit design from RTL-GDS for CPU and SoC, circuit simulation, equivalence checking, PPA trade off analysis, low power design techniques, timing, noise and power characterization.
• Prior experience and proven success of successfully designing high performance SRAM memories, Register file memories, SRAM compilers, data path designs and standard cells
• Experience designing transistor-level custom circuits in advanced FinFET technology nodes
• Solid understanding of device physics, process technology and circuit design techniques for high performance, low power
• Experience with advanced process design rules and supervising mask design
• Knowledge developing automation for compilers and standard cells
• Post-Silicon test and debug experience
• Ability to work well in a team and be productive under aggressive schedules.
• Excellent problem solving, written and verbal communication

Education and Experience

• Master's Degree or Bachelor's Degree with 7+ years of experience

Extensive hands on and teaching experience on Digital / SV /UVM/ Verilog / VHDL /DFT tools

Extensive experience in Back-end design

Experience on Mentor Graphics EDA flow is an added advantage

Responsible for development and support of Projects.

Responsible for Debugging the source codes in Verilog, SV, and UVM.

Responsible for Training Delivery and Support

Sound Knowledge on Digital / Verilog / VHDL / SV / UVM / DFT / Back-end design

3 to 8 years industry/teaching experience

Good communication skill

alog Circuit Design::

• The candidate should have B.Tech or M.Tech in Electronics/Electrical/VLSI Design Engineering
• The candidate should have relevant work experience of 7-16 years in Analog and SERDES IO IP design e.g. GPIOs, Thermal Sensor, PLL, ADC/DAC/ Voltage regulators/LDOs, AIB, HBMIO, DDR, HDMI/DP IO, MIPI IO etc.