Member Technical Staff at maven silicon · Bengaluru (Bangalore) · 1 - 8 years · ₹2.5L - ₹7L / yr · Profitable · Posted 19 Jan 2023
Job Description
Extensive hands on and teaching experience on Digital / SV /UVM/ Verilog / VHDL /DFT tools
Extensive experience in Back-end design
Experience on Mentor Graphics EDA flow is an added advantage
Responsible for development and support of Projects.
Responsible for Debugging the source codes in Verilog, SV, and UVM.
Responsible for Training Delivery and Support
Desired Candidate Profile
Sound Knowledge on Digital / Verilog / VHDL / SV / UVM / DFT / Back-end design
3 to 8 years industry/teaching experience
Good communication skill
Shubham Vishwakarma
Full Stack Developer - Averlon
About maven silicon
About
Company social profiles
Similar jobs (2)
We are hiring a VLSI Design Engineer to work on chip design and verification.
Responsibilities
- Write and verify RTL in Verilog and SystemVerilog
- Work on synthesis, timing analysis or physical design
- Debug designs and fix timing and functional issues
- Work with verification and backend teams through tape-out
Requirements
- 1+ years of VLSI or ASIC design experience
- Strong Verilog or SystemVerilog skills
- Familiarity with EDA tools (Synopsys or Cadence)
Hello Everyone
ElevarSoC hiring for Bangalore, Hyderabad locations
3-6 years of experience with Good DFT concepts in SCAN INSERTION, ATPG and Simulations.
Good exposure to Synth, ATPG tools (Mentor) : DRC & coverage analysis, Timing/no timing (VCS) simulations.
Anyone already worked for Qcomm/product company is preferable.
Candidate should be independent in handling the given task.
Mandatory Skills:
ATPG trace (DRC), Stuck at and TDF Coverage Analysis
ATPG no timing and timing vector simulations
Apply now!!
Follow CutshortShubham Vishwakarma
Full Stack Developer - Averlon