Principal Engineer – Physical Design (SoC / RTL to GDSII) at Frequencycx · Bengaluru (Bangalore) · 15 - 17 years · ₹25L - ₹60L / yr · Bootstrapped · Posted 8 Apr 2026

We are hiring a Principal Engineer – Physical Design to lead end-to-end implementation of advanced-node SoCs (7nm and below), from RTL to GDSII.
Key Responsibilities:
- Lead SoC / full-chip physical design and integration
- Drive floorplanning, partitioning, and P&R (APR)
- Define chip-level architecture for performance, power, and area
- Own clocking strategy, power planning, and dataflow
- Handle IO ring design, bump planning, and package co-design
- Ensure physical verification closure (DRC, LVS, DFM)
- Develop and own P&R flows and methodologies
- Collaborate with cross-functional teams (architecture, RTL, packaging)
- Mentor junior engineers and lead execution
Requirements:
- 15+ years in VLSI Physical Design
- Experience in 7nm or below technology nodes
- Strong expertise in floorplanning, STA, and P&R
- Hands-on with tools like ICC2 / Innovus / PrimeTime
- Experience in full-chip SoC tape-outs
- Strong understanding of ESD, latch-up, and foundry rules
- Experience with package integration and RDL is a plus

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We are hiring a VLSI Design Engineer to work on chip design and verification.
Responsibilities
- Write and verify RTL in Verilog and SystemVerilog
- Work on synthesis, timing analysis or physical design
- Debug designs and fix timing and functional issues
- Work with verification and backend teams through tape-out
Requirements
- 1+ years of VLSI or ASIC design experience
- Strong Verilog or SystemVerilog skills
- Familiarity with EDA tools (Synopsys or Cadence)
Hello Everyone
ElevarSoC hiring for Bangalore, Hyderabad locations
3-6 years of experience with Good DFT concepts in SCAN INSERTION, ATPG and Simulations.
Good exposure to Synth, ATPG tools (Mentor) : DRC & coverage analysis, Timing/no timing (VCS) simulations.
Anyone already worked for Qcomm/product company is preferable.
Candidate should be independent in handling the given task.
Mandatory Skills:
ATPG trace (DRC), Stuck at and TDF Coverage Analysis
ATPG no timing and timing vector simulations
Apply now!!

Interested in designing award-winning wearables while managing challenging constraints so that your products are used everyday by millions of users? Then read on..
ULTRAHUMAN • HARDWARE
Hardware Design Engineer Wearables
Bangalore (Kudlu Gate)| • On-site | Full-time |
ABOUT THE ROLE
Ultrahuman's Hardware division builds award-winning wearables the Ultrahuman Ring and Ring Air pushing consumer technology in health and metabolic fitness. We're looking for a Hardware Design Engineer to own electronics design for our next-generation smart rings, from architecture and schematic capture through PCB layout, bring-up, and mass production.
This is a hands-on role at the extremes of miniaturization and power efficiency. You'll make architecture-level component decisions, drive high-density and RF layout, and take designs through NPI to volume — working closely with mechanical, firmware, and manufacturing teams on fast product cycles.
KEY RESPONSIBILITIES
Architecture & Schematic Design
- Translate product requirements into hardware architecture, then into schematics and manufacturable PCB designs using OrCAD / Allegro (Cadence).
- Own component selection across MCU/SoC, PMIC, sensor AFEs, and RF front-ends — balancing size, power, cost, and supply availability.
- Handle schematic-to-layout conversion and netlist import; create and maintain symbol/footprint libraries and land patterns.
High-Density & RF Layout
- Design and review high-density (HDI), rigid, and rigid-flex PCB layouts for space-constrained wearable form factors.
- Design 2.4 GHz BLE antennas and NFC coils, matching networks, and controlled-impedance routing; support antenna tuning and RF validation.
- Apply signal-integrity best practices for high-speed digital interfaces and mixed-signal boards.
Power & Low-Power Design
- Architect power trees around PMICs, buck/boost converters, and LDOs, including Li-ion charging for small-capacity cells.
- Build and validate ultra-low-power current budgets to meet multi-day battery-life targets.
- Strong grasp of power electronics and active/passive component behaviour.
Sensor Integration
- Integrate optical biosensing (PPG) AFEs, IMUs, temperature sensors, and haptics; own I²C/SPI interface design and analog front-end layout.
Manufacturing & DFM
- Own Gerber/ODB++ release, fabrication and assembly drawings, panelization, and full manufacturing data packages.
- Prepare and maintain BOMs; evaluate and qualify alternate / second-source components.
- Drive DFM/DFA reviews with fab and SMT/EMS partners; support NPI through EVT/DVT/PVT to mass production.
- Sound understanding of PCB materials, stackups, and component assembly processes.
Compliance, Reliability & Validation
- Apply EMI/EMC, thermal, and mechanical design best practices.
- Support pre-compliance and certification across FCC, CE, BIS, and RoHS, and familiarity with IEC standards for PCB design safety.
- Coordinate with test engineers on board bring-up and PCB validation; run circuit simulations for RF and signal/timing optimization.
Ownership & Collaboration
- Independently manage hardware projects end-to-end, including vendor coordination and delivery of final hardware.
- Collaborate with mechanical engineers to optimize designs and meet project timelines.
- Bring the latest design tools, methodologies, and industry best practices into the team.
REQUIRED QUALIFICATIONS
- Bachelor's or Master's in EEE, Electronics, or equivalent practical experience.
- 4+ years of hands-on hardware / PCB design experience, ideally in consumer electronics or wearables.
- Proficiency with a leading schematic and PCB toolchain (OrCAD / Allegro preferred).
- Proven track record taking a product from schematic through layout to volume production.
- Working knowledge of power electronics and active/passive component selection.
- Familiarity with global certifications (FCC, CE, BIS, RoHS) and IEC PCB safety standards.
PREFERRED / BONUS
- Experience with miniaturized high-density or rigid-flex designs.
- RF design experience (2.4 GHz / BLE, NFC, antenna tuning and matching).
- EMI/EMC design and pre-compliance testing experience.
- Low-power / battery-operated wearable product experience.
- Familiarity with reliability methods (DFMEA, derating) and RF / signal-timing circuit simulation.





