Custom Memory Design
SRAM/custom circuit design and standard cell design
Qualifications • Candidates must have 7+ years of experience in transistor level custom circuit design from RTL-GDS for CPU and SoC, circuit simulation, equivalence checking, PPA trade off analysis, low power design techniques, timing, noise and power characterization • Prior experience and proven success of successfully designing high performance SRAM memories, Register file memories, SRAM compilers, data path designs and standard cells • Experience designing transistor-level custom circuits in advanced FinFET technology nodes • Solid understanding of device physics, process technology and circuit design techniques for high performance, low power • Experience with advanced process design rules and supervising mask design • Knowledge developing automation for compilers and standard cells • Post-Silicon test and debug experience • Ability to work well in a team and be productive under aggressive schedules • Excellent problem solving, written and verbal communication • Master's Degree or Bachelor's Degree with 7+ years of experience |
Responsibilities • The role will be at the center of a state-of-the-art circuit design effort, interfacing with all disciplines and have a critical impact on getting products to market quickly • Responsible for designing and delivering custom circuits from scratch • Drive design and development of SRAM, register file, custom cells to enable high performance and low power designs • Work with microarchitecture team to gather specifications • Drive optimal implementation Conduct early sizing estimates and PPA analysis • Perform design entry and simulations for optimal design sizing • Work closely with mask designers on custom design implementation, DFM and yield enhancement features • Collaborate with the CPU and SoC Physical design teams on floorplanning, placement, timing and power closure of the custom design • Interact with technology team • Participate in developing design and test plans Collaborate with the CAD team and drive design flow enhancements |
Job description
Rivos Custom Circuits team is seeking highly motivated candidates to develop state of the art custom SRAM memories, Register file memories, memory compilers and standard cells to improve circuit performance, optimize dynamic and static power and support silicon bring up. The role will be at the center of a state-of-the-art circuit design effort, interfacing with all disciplines and have a critical impact on getting products to market quickly.
Responsibilities
- Responsible for designing and delivering custom circuits from scratch.
- Drive design and development of SRAM, register file, custom cells to enable high performance and low power designsWork with microarchitecture team to gather specifications
- Drive optimal implementation Conduct early sizing estimates and PPA analysis. Perform design entry and simulations for optimal design sizingWork closely with mask designers on custom design implementation, DFM and yield enhancement featuresCollaborate with the CPU and SoC Physical design teams on floorplanning, placement, timing and power closure of the custom designInteract with technology team
- Participate in developing design and test plans Collaborate with the CAD team and drive design flow enhancements
Qualification
- Candidates must have 7+ years of experience in transistor level custom circuit design from RTL-GDS for CPU and SoC, circuit simulation, equivalence checking, PPA trade off analysis, low power design techniques, timing, noise and power characterization.
- Prior experience and proven success of successfully designing high performance SRAM memories, Register file memories, SRAM compilers, data path designs and standard cells
- Experience designing transistor-level custom circuits in advanced FinFET technology nodes
- Solid understanding of device physics, process technology and circuit design techniques for high performance, low power
- Experience with advanced process design rules and supervising mask design
- Knowledge developing automation for compilers and standard cells
- Post-Silicon test and debug experience
- Ability to work well in a team and be productive under aggressive schedules.
- Excellent problem solving, written and verbal communication
Education and Experience
- Master's Degree or Bachelor's Degree with 7+ years of experience
About Rivos Inc
Similar jobs
we are hiring for memory design
experience: 4+yrs
location: remote
skills required:
- Sound Knowledge of SRAM Memory compiler and memory instance Design
- Design Validations e.g. Design Margin closure, SA and Self Time Analysis
- Timing and Power characterization
- Communication skill
Responsibilities
- Responsible for design and spec development and design of analog blocks for advanced mixed-signal / analog circuits.
- Write detailed design specification and will be in close collaboration with the system architect, circuit designers and design verification engineers.
- Work on behavioral modeling of analog blocks and support design verification to ensure bug free silicon.
- Lead development of analog blocks in collaboration with external vendors and lead integration, test plan and characterization efforts.
Requirements
- Strong track record of architect, develop, verification and validation of complete silicon IPs
- Deep understanding of bandgaps, bias, opamps, switched-cap circuits, LDOs, PLLs, feedback and compensation techniques, DCDC converters
- In-depth knowledge and good understanding of analog design techniques.
- Experience in digital integration of analog IPs with chip level integration team
- Experience in developing behavior modeling a plus
- Experience IP design management or vendor management a plus
- Strong device physics knowledge as it applies to analog IC design
- Hand-on experience with IP lab characterization using spectrum analyzers, oscilloscopes, signal generators, etc.
- Experience in working with production test engineers to produce test plans and design for testability details
- Excellent communication skills
- Team player with an ability to encourage team members
Education & Experience
- MS (preferred in EE) plus 8 years
- PhD (preferred in EE) plus 5 years
Note:
Annual job salary: The annual job salary mentioned in this posting is a default number taken by cutshort and is inaccurate. <Not mentioned/ disclosed by Rivos>
Resumes:
Interested folks with 3+ years to 20 years of experience into AMS Design, Please reach out to the Recruiter Deepa Savant to learn more about the job and discuss details.
Key qualifications•
The ideal candidate will have 4+ years of experience in backend design automation and standard cell characterization
• Prior experience and proven success of successfully designing high performance standard cells is desired
• Solid knowledge of circuit analysis, reliability, extraction, and SPICE simulation to validate design performance
• Knowledge of industry standard hardware design CAD software and required standard cell design view generation and validation.
• Solid foundation of scripting fluency in TCL, Perl/Python
• Basic knowledge of advanced FinFet device and standard cell circuit and layout
• Ability to work well in a team and be productive under aggressive schedules.
• Excellent problem solving, written and verbal communicationResponsibilities• Responsible for timing and power characterization and generation of standard cell EDA views,
• Other job duties include performing QA including EM/IR and design checks
• adding automation to improve design productivity
Note:
Annual job salary: The annual job salary mentioned in this posting is a default number taken by cutshort and is inaccurate. <Not mentioned/ disclosed by Rivos>
Resumes:
Interested folks with 4+ years of experience in Standard cell, Please reach out to the Recruiter Deepa Savant to learn more about the job and discuss details.
alog Circuit Design::
- The candidate should have B.Tech or M.Tech in Electronics/Electrical/VLSI Design Engineering
- The candidate should have relevant work experience of 7-16 years in Analog and SERDES IO IP design e.g. GPIOs, Thermal Sensor, PLL, ADC/DAC/ Voltage regulators/LDOs, AIB, HBMIO, DDR, HDMI/DP IO, MIPI IO etc.
Skills/Experience
Experience with complete flows involving timing closure of high speed digital design using scripting languages and design automation.
Has deep knowledge of Xilinx FPGA implementation and tools.
Experience in state of the art tools and flows.
Working knowledge in Verilog and System Verilog.
Job Requirements
Bachelors in Electronics Engineering.
Strong knowledge of ASIC and/or FPGA design methodology and should be well versed in front-end design, simulation, and verification CAD tools.
Relevant FPGA/ASIC engineering design and verification experience is entertained.
Excellent verbal, written and communication skills are required.
Excellent follow-through, motivation, and persistence
Strong technical judgment and decision making abilities.
Knowledge of digital board design and signal integrity principles is a plus.