Rivos Inc
https://rivosinc.comAbout
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Jobs at Rivos Inc
The recruiter has not been active on this job recently. You may apply but please expect a delayed response.
Responsibilities
- Schematic capture, board block design, defining routing constraints, layout review, and simulation
- System design for chip bring-up boards and final systems
- Lab bring-up, test, and debugging
- Co-designing with power and signal integrity analysis specialists
- High-speed interface characterization
- Debugging system-level issues
- Resolving system-level issues related to silicon validation and characterization
- Work with ODMs to facilitate the NPI (New Product Introduction) process
Requirements
- Experience designing SoC/CPU boards (schematic, layout, manufacturing, debug)
- Familiarity with a variety of board-level interfaces: I2C, SPI, DDR, etc
- Knowledge of high-speed, high-power, system design
- Design and analysis of power supplies
- CPU/SoC/Microcontroller system architecture familiarity
- Test automation expertise using Python or other languages
- Board-level analog and digital circuit design expertise
- HDL experience is a plus
- Excellent skills in problem-solving, written and verbal communication, excellent organization skills, and highly self-motivated.
- Ability to work well in a team and be productive under aggressive schedules.
- Desire to learn new skills and attack novel problems.
- Able to travel to ODM’s factory and/or Rivos’s oversea office for on-site support and meetings
Education and Experience
- Master’s Degree or Bachelor’s Degree in the technical subject area.
Note
Annual job salary: The annual job salary mentioned in the posting is a default number taken by cutshort and is inaccurate.
Resumes
Interested folks with 3+ years of experience, Please reach out to the Job Poster to learn more about the job and discuss details.
The recruiter has not been active on this job recently. You may apply but please expect a delayed response.
Responsibilities
- Responsible for performing verification for AMS designs.
- Create UVM benches for mixed signal blocks and developing test scenarios.
- Work closely with the architecture and design teams on verification plan and methodology to achieve complete verification coverage
- Write assertions and checkers for the properties and corner cases
- Analyze verification coverage and improve the test cases
- Integrate analogue design IPs from vendors and internal teams and develop verification environments for simulation and emulation
Requirements
- Detailed knowledge of verification using SystemVerilog
- Experience with creating UVM based testbenches for Analog Mixed-Signal applications
- Experience with assertion based verification for analog blocks
- Experience with power aware verification with UPF will be a plus
- UVM-AMS experience preferred
- Experience with sv-real preferred
- Scripting skills in perl / python is preferred
- Excellent communication skills
- Team player with an ability to encourage team members
Education & Experience
- MS (preferred in EE and CE) plus 5 years
Note:
Annual job salary: The annual job salary mentioned in this posting is a default number taken by cutshort and is inaccurate. <Not mentioned/ disclosed by Rivos>
Resumes:
Interested folks with 5+ years to 20 years of experience into AMS Verification, Please reach out to the Recruiter Deepa Savant to learn more about the job and discuss details.
The recruiter has not been active on this job recently. You may apply but please expect a delayed response.
Responsibilities
- Responsible for design and spec development and design of analog blocks for advanced mixed-signal / analog circuits.
- Write detailed design specification and will be in close collaboration with the system architect, circuit designers and design verification engineers.
- Work on behavioral modeling of analog blocks and support design verification to ensure bug free silicon.
- Lead development of analog blocks in collaboration with external vendors and lead integration, test plan and characterization efforts.
Requirements
- Strong track record of architect, develop, verification and validation of complete silicon IPs
- Deep understanding of bandgaps, bias, opamps, switched-cap circuits, LDOs, PLLs, feedback and compensation techniques, DCDC converters
- In-depth knowledge and good understanding of analog design techniques.
- Experience in digital integration of analog IPs with chip level integration team
- Experience in developing behavior modeling a plus
- Experience IP design management or vendor management a plus
- Strong device physics knowledge as it applies to analog IC design
- Hand-on experience with IP lab characterization using spectrum analyzers, oscilloscopes, signal generators, etc.
- Experience in working with production test engineers to produce test plans and design for testability details
- Excellent communication skills
- Team player with an ability to encourage team members
Education & Experience
- MS (preferred in EE) plus 8 years
- PhD (preferred in EE) plus 5 years
Note:
Annual job salary: The annual job salary mentioned in this posting is a default number taken by cutshort and is inaccurate. <Not mentioned/ disclosed by Rivos>
Resumes:
Interested folks with 3+ years to 20 years of experience into AMS Design, Please reach out to the Recruiter Deepa Savant to learn more about the job and discuss details.
The recruiter has not been active on this job recently. You may apply but please expect a delayed response.
PythonResponsibilities
- Define DFT strategy and methodologies
- Design the DFT features
- Define test structures, debug structures, and test plans
- Create test vectors or oversee their creation
- Collaborate with physical design team to close requirements
- Validate DFT requirements are being met
- Work with designers to increase test coverage, debug observability and flexibility
- Verify post-PD designs meet DFT requirements
- Work with verification engineers, stepping in to do run tests when needed
Requirements
- Good knowledge of digital logic design, microprocessor, debug feature, DFT architecture, CPU architecture, and microarchitecture
- Knowledge of DFT and structural debug concepts and methodologies: JTAG, IEEE1500, MBIST, scan dump, memory dump
- Knowledge of Verilog and experience with simulators and waveform debugging tools
- Knowledge of Verilog / SystemVerilog
- Knowledge of Python, , Shell scripting, Makefiles, TCL a plus
- Excellent skills in problem solving, written and verbal communication, excellent organization skills, and highly self-motivated.
- Ability to work well in a team and be productive under aggressive schedules.
Note:
Annual job salary: The annual job salary mentioned in this posting is a default number taken by cutshort and is inaccurate. <Not mentioned/ disclosed by Rivos>
Resumes:
Interested folks with 3+ years of experience to 20 years of experience into Silicon DFT, Please reach out to the Recruiter Deepa Savant to learn more about the job and discuss details.
The recruiter has not been active on this job recently. You may apply but please expect a delayed response.
Responsibilities
- Work closely with architecture and RTL designers on verifying the functionality correctness of the design
- Reviewing Architecture and Design Specifications
- Develop test plans and test environments
- Develop tests in assembly, C/C++, or vectors according to test plans
- Develop coverage monitors and analyze coverage to ensure all the test cases in the plans are covered
- Develop checkers in SystemVerilog or C-base transactors to verify the design
- Write assertions and apply formal verification to the designImplementing test benches, generating directed/constrained random tests
- Debugging failures, running simulations, tracking bugs
- Handling schedules and supporting multi-functional engineering effortAssisting in verification flows, automation scripts and regressions
Requirements
- In-depth knowledge of digital logic design, CPU/SOC architecture and microarchitecture.
- Sophisticated knowledge of SystemVerilog.
- Experienced level knowledge C/C++.Relevant knowledge of verification methodologies and tools such as simulators, waveform viewers, build and run automation, coverage collection.
- Basic knowledge of formal verification methodology is a plus.
- Excellent knowledge of one of the scripting languages such as Python, TCL is a plus.
- Excellent skills in problem solving, written and verbal communication, excellent organization skills, and highly self-motivated.
- Ability to work well in a team and be productive under aggressive schedules.
Education and Experience
- PhD, Master’s Degree or Bachelor’s Degree in technical subject area.
Note:
Annual job salary: The annual job salary mentioned in this posting is a default number taken by cutshort and is inaccurate. <Not mentioned/ disclosed by Rivos>
Resumes:
Interested folks with 2+ years to 20 years of experience into Silicon CPU or SOC Verification, Please reach out to the Recruiter Deepa Savant to learn more about the job and discuss details.
The recruiter has not been active on this job recently. You may apply but please expect a delayed response.
Join the most cutting-edge and well-funded hardware startup in Silicon Valley as a CAD Engineer. Our mission is to reimagine silicon and create computing platforms that will transform the industry. You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. We offer a fun, creative and flexible work environment, with a shared vision to build products to change the world.
Responsibilities
- Work with chip leads to understand the logic design and verification methodology and high level requirements in support of RTL design
- Collaborate with chip leads to determine other areas to support current or future designs that can benefit from automation and tooling
- Define and implement new infrastructure capabilities, tool flows, and environments that can be used to accelerate design and development
Requirements
- Strong fundamentals in digital ASIC design; experience using SystemVerilog
- Strong skills in various front end design tools and techniques such as logic equivalence, lint checks, clock and reset domain crossing and DFT
- Knowledge of SOC/CPU architecture
- Familiarity with high performance and low power design techniques
- Hands on experience in digital design
- Excellent skills in problem solving, written and verbal communication, excellent organization skills, and highly self-motivated
- Ability to work well in a team and be productive under aggressive schedules.
Education and Experience
- PhD, Master’s Degree or Bachelor’s Degree in technical subject area.
Note:
Annual job salary: The annual job salary mentioned in this posting is a default number taken by cutshort and is inaccurate. <Not mentioned/ disclosed by Rivos>
Resumes:
Interested folks with 3+ years of experience to 20 years of experience into Silicon CAD, Please reach out to the Recruiter Deepa Savant to learn more about the job and discuss details.
The recruiter has not been active on this job recently. You may apply but please expect a delayed response.
Key qualifications•
The ideal candidate will have 4+ years of experience in backend design automation and standard cell characterization
• Prior experience and proven success of successfully designing high performance standard cells is desired
• Solid knowledge of circuit analysis, reliability, extraction, and SPICE simulation to validate design performance
• Knowledge of industry standard hardware design CAD software and required standard cell design view generation and validation.
• Solid foundation of scripting fluency in TCL, Perl/Python
• Basic knowledge of advanced FinFet device and standard cell circuit and layout
• Ability to work well in a team and be productive under aggressive schedules.
• Excellent problem solving, written and verbal communicationResponsibilities• Responsible for timing and power characterization and generation of standard cell EDA views,
• Other job duties include performing QA including EM/IR and design checks
• adding automation to improve design productivity
Note:
Annual job salary: The annual job salary mentioned in this posting is a default number taken by cutshort and is inaccurate. <Not mentioned/ disclosed by Rivos>
Resumes:
Interested folks with 4+ years of experience in Standard cell, Please reach out to the Recruiter Deepa Savant to learn more about the job and discuss details.
The recruiter has not been active on this job recently. You may apply but please expect a delayed response.
Custom Memory Design
SRAM/custom circuit design and standard cell design
|
Qualifications • Candidates must have 7+ years of experience in transistor level custom circuit design from RTL-GDS for CPU and SoC, circuit simulation, equivalence checking, PPA trade off analysis, low power design techniques, timing, noise and power characterization • Prior experience and proven success of successfully designing high performance SRAM memories, Register file memories, SRAM compilers, data path designs and standard cells • Experience designing transistor-level custom circuits in advanced FinFET technology nodes • Solid understanding of device physics, process technology and circuit design techniques for high performance, low power • Experience with advanced process design rules and supervising mask design • Knowledge developing automation for compilers and standard cells • Post-Silicon test and debug experience • Ability to work well in a team and be productive under aggressive schedules • Excellent problem solving, written and verbal communication • Master's Degree or Bachelor's Degree with 7+ years of experience |
Responsibilities • The role will be at the center of a state-of-the-art circuit design effort, interfacing with all disciplines and have a critical impact on getting products to market quickly • Responsible for designing and delivering custom circuits from scratch • Drive design and development of SRAM, register file, custom cells to enable high performance and low power designs • Work with microarchitecture team to gather specifications • Drive optimal implementation Conduct early sizing estimates and PPA analysis • Perform design entry and simulations for optimal design sizing • Work closely with mask designers on custom design implementation, DFM and yield enhancement features • Collaborate with the CPU and SoC Physical design teams on floorplanning, placement, timing and power closure of the custom design • Interact with technology team • Participate in developing design and test plans Collaborate with the CAD team and drive design flow enhancements |
Job description
Rivos Custom Circuits team is seeking highly motivated candidates to develop state of the art custom SRAM memories, Register file memories, memory compilers and standard cells to improve circuit performance, optimize dynamic and static power and support silicon bring up. The role will be at the center of a state-of-the-art circuit design effort, interfacing with all disciplines and have a critical impact on getting products to market quickly.
Responsibilities
- Responsible for designing and delivering custom circuits from scratch.
- Drive design and development of SRAM, register file, custom cells to enable high performance and low power designsWork with microarchitecture team to gather specifications
- Drive optimal implementation Conduct early sizing estimates and PPA analysis. Perform design entry and simulations for optimal design sizingWork closely with mask designers on custom design implementation, DFM and yield enhancement featuresCollaborate with the CPU and SoC Physical design teams on floorplanning, placement, timing and power closure of the custom designInteract with technology team
- Participate in developing design and test plans Collaborate with the CAD team and drive design flow enhancements
Qualification
- Candidates must have 7+ years of experience in transistor level custom circuit design from RTL-GDS for CPU and SoC, circuit simulation, equivalence checking, PPA trade off analysis, low power design techniques, timing, noise and power characterization.
- Prior experience and proven success of successfully designing high performance SRAM memories, Register file memories, SRAM compilers, data path designs and standard cells
- Experience designing transistor-level custom circuits in advanced FinFET technology nodes
- Solid understanding of device physics, process technology and circuit design techniques for high performance, low power
- Experience with advanced process design rules and supervising mask design
- Knowledge developing automation for compilers and standard cells
- Post-Silicon test and debug experience
- Ability to work well in a team and be productive under aggressive schedules.
- Excellent problem solving, written and verbal communication
Education and Experience
- Master's Degree or Bachelor's Degree with 7+ years of experience
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About the company
About Us
Incubyte is an AI-first software development agency, built on the foundations of software craft, where the “how” of building software matters as much as the “what”. We partner with companies of all sizes, from helping enterprises build, scale, and modernize; to pre-product founders bring their ideas to life.
Incubees are power users of AI across the SDLC for speed and efficiency. Guided by Software Craftsmanship values and eXtreme Programming practices, we bring velocity together with the discipline of quality engineering to deliver high-impact, reliable solutions – fast.
Guiding Principles
- Living and breathing our guiding principles on a daily basis is key to success at Incubyte:
- Relentless Pursuit of Quality with Pragmatism
- Striving for exceptional quality without losing sight of practical delivery needs.
- Extreme Ownership Taking full responsibility for decisions, work, and outcomes.
- Proactive Collaboration Actively seeking opportunities to collaborate and leverage the team’s collective strengths.
- Active Pursuit of Mastery Continuously learning, improving, and mastering the craft, never settling for ‘good enough’.
- Invite, Give, and Act on Feedback
- Creating a culture of timely, respectful, actionable feedback for mutual growth.
- Ensuring Client Success Acting as trusted consultants and focusing on delivering true value and outcomes for clients.
Job Description
This is a remote position
Experience Level
This role is ideal for engineers with 5+ years of total experience, including strong hands-on software development experience and 1+ year of technical leadership experience, with a proven track record of shipping complex projects successfully.
An experienced individual contributor and leader who thrives in large, complex projects with widespread impact.
Role Overview
As a Senior Engineer, you’ll ensure that projects don’t just get built — they get shipped. You’ll be the driving force behind architecture design, technical decision-making, project delivery, and stakeholder communication.
A Senior Craftsperson is a multiplier for any team:
- Able to independently own ill-defined, highly ambiguous projects.
- Thinks holistically across Product, Design, Platform, and Operations to deliver highly impactful solutions.
- Shapes roadmaps to tackle complex problems incrementally.
- Raises the quality, correctness, and suitability of their team’s work, with visible impact across their business domain and beyond.
- Strong mentor, role model, and coach for other engineers.
If you take pride in shipping high-quality software, mentoring teams, and creating an environment where engineers can thrive, we’d love to hear from you.
What You’ll Do
- Lead projects end-to-end, from architecture to deployment, ensuring timely, high-quality delivery.
- Collaborate with Engineering and Product Managers to plan, scope, and break work into manageable tasks.
- Always know if the project can ship, with clear trade-offs when needed.
- Drive technical decisions with a shipping-first mindset and active participation in key meetings.
- Maintain deep knowledge of your services, identifying risks and creating mitigation strategies.
- Review code for quality and best practices, mentoring engineers to improve their craft.
- Communicate clearly with stakeholders, set realistic expectations, and build trust.
- Support and guide engineers, helping unblock issues and foster collaboration.
- Anticipate challenges, prepare fallback plans, and facilitate problem-solving.
- Keep documentation accurate, up-to-date, and accessible.
You will also:
- Lead highly ambiguous projects of critical business impact, balancing engineering, operational, and client priorities.
- Link technical contributions directly to business impact, helping the team and stakeholders align.
- Contribute meaningfully to team goals, with visibility into business objectives over multiple quarters.
- Ensure safe rollout of new features through incremental releases, monitoring, and metrics.
- Anticipate and mitigate risks across connected systems, ensuring minimal operational impact.
- Proactively improve system quality and longevity while leveling up those around you.
- Shape roadmaps, vision, and practices of the engineering discipline, influencing both your team and the wider business.
Requirements
What We’re Looking For
- 5+ years of software development experience, with strong architectural design skills.
- Strong hands-on experience with Python and PHP (must-have) and react.js (good-have).
- 1+ year in a technical leadership role, managing pods or cross-functional teams.
- Proficiency in system design, service ownership, and technical documentation.
- Strong experience with code reviews and quality assurance practices.
- Proven ability to communicate effectively with technical and non-technical stakeholders.
- Track record of delivering complex projects on time.
You will also bring:
- Ability to own large, complex projects with widespread impact.
- Demonstrated influence beyond the immediate team, shaping outcomes across a business domain.
- Strengths in stakeholder management and navigating complex scenarios.
- Skills in deliberate discovery to uncover unknowns and design solutions that succeed in real-world conditions.
Benefits
What We Offer
Dedicated Learning & Development Budget: Fuel your growth with a budget dedicated solely to learning.
Conference Talks Sponsorship: Amplify your voice! If you’re speaking at a conference, we’ll fully sponsor and support your talk.
Cutting-Edge Projects: Work on exciting projects with the latest AI technologies
Employee-Friendly Leave Policy: Recharge with ample leave options designed for a healthy work-life balance.
Comprehensive Medical & Term Insurance: Full coverage for you and your family’s peace of mind.
And More: Extra perks to support your well-being and professional growth.
Work Environment
- Remote-First Culture: At Incubyte, we thrive on a culture of structured flexibility — while you have control over where and how you work, everyone commits to a consistent rhythm that supports their team during core working hours for smooth collaboration and timely project delivery. By striking the perfect balance between freedom and responsibility, we enable ourselves to deliver high-quality standards our customers recognize us by. With asynchronous tools and push for active participation, we foster a vibrant, hands-on environment where each team member’s engagement and contributions drive impactful results.
- Work-In-Person: Twice a year, we come together for two-week sprints to collaborate in person, foster stronger team bonds, and align on goals. Additionally, we host an annual retreat to recharge and connect as a team. All travel expenses are covered.
- Proactive Collaboration: Collaboration is central to our work. Through daily pair programming sessions, we focus on mentorship, continuous learning, and shared problem-solving. This hands-on approach keeps us innovative and aligned as a team.
Incubyte is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.
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Funding Journey
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Our Values
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- We have a Championship Mindset: We operate like a professional sports team. We win as a team by holding ourselves and each other to high standards, collaborating in-person, and remaining focused on the mission.
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- We Work for the Customer: We focus on delivering outsized value to the customers we work with and expanding those relationships to deep, meaningful partnerships.
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