2+ RTL Jobs in Bangalore (Bengaluru) | RTL Job openings in Bangalore (Bengaluru)
Apply to 2+ RTL Jobs in Bangalore (Bengaluru) on CutShort.io. Explore the latest RTL Job opportunities across top companies like Google, Amazon & Adobe.
About the organization
QFocus AI Pvt. Ltd. (QFAI), a wholly owned subsidiary of QFocus Technologies LLC, is a consulting-led engineering services company with sharp focus on supporting next gen advanced products development across AI/ML, Compute, Communication, Storage and Consumer Electronics. Our mission is to help our customers deliver cutting-edge products on time ensuring world-class quality.
Why Join QFAI? Join a passionate team, dedicated to making a difference.
We are a close-knit team, with strong mission, vision and values that guide our day-to-day. Recognition of work, respect, and our multicultural community are key aspects of the employee experience and contribute to our continued success. Would you like to be part of our story? Don't hesitate, come and join us!
About this opportunity – Formal Verification Engineer
We are seeking a highly skilled and passionate Formal Verification Engineer to join our team working with the best in the Industry, developing innovative ASIC solutions for data center and AI Infrastructure. The ideal candidate will develop comprehensive formal test plans and be responsible for complete formal verification sign-off of single or multiple complex blocks. The role also provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC Design, Emulation and Post-Silicon teams towards creating a first-pass silicon success.
Key Responsibilities:
· Contribute to Formal Verification applying and evangelizing state of the art Formal Verification Methodologies across IP-level, subsystem-level and SOC Level.
· Collaborate with Architecture and Design teams to develop formal specifications and implementations.
· Define formal verification scope, create formal environments, and achieve coverage sign-off using targeted formal verification techniques.
· Develop comprehensive formal test plans, including unique security requirement verification.
· Build reusable and scalable formal verification environments and deploy relevant tools.
· Evaluate and recommend EDA solutions for Formal Verification and drive improvements to methodologies and flows.
· Debug complex issues in RTL designs based on formal results and contribute to design improvements.
Required Skills:
- Strong hands-on experience with Formal Verification tools (e.g., JasperGold, VC-Formal, Questa Formal).
- Experience writing formal properties using System Verilog Assertions (SVA) or Property Specification Language (PSL).
- Proven understanding of Formal Verification methodologies, complexity reduction techniques, and abstraction techniques.
- Fluency in hardware description languages, such as SystemVerilog.
- Proficiency in scripting languages such as Python, Perl, or Tcl within Unix/Linux environments.
Education:
Bachelor's degree in Computer Science, Computer Engineering, Electrical Engineering, or a related technical field, or equivalent practical experience.
Experience:
5+ years of experience in Design Verification, with at least 1 year in Formal Verification.
QFocus AI Pvt Ltd is an Equal Employment Opportunity employer.
InnoPhase Bangalore is looking for a Senior Engineer, Digital Physical Design to join a growing start
up semiconductor development organization and to help drive excellence in our IoT products.
Roles & Responsibilities
Design, Develop and execute physical design implementation of low-power and high-performance SoC, including
logic synthesis, floorplan and power plan, power domain specification, place and route, clock tree synthesis, static
timing analysis, IR drop analysis, EM, and physical verification in advanced technology nodes.
- Work with the RTL and System design teams to drive the physical design of the device in the early design cycle.
- Design, implement and verify suitable methodology that meets the QoR goals.
- Resolve design and flow issues related to the physical design, identify potential solutions, and drive
- Deliver physical design of entire SoC, complete with specification, flow and automation.
- Interface with the RTL design team to drive design modifications to resolve physical design issues and
- Use EDA tool-based programming and scripting techniques to automate and improve throughput and quality.
- Interact with tool vendors to drive tool fixes and flow improvements. Perform tool evaluations of new
Desired Qualities
- Bachelor’s degree (Master’s preferred) in Electrical Engineering or comparable engineering discipline.
- 5 to 8 years of relevant experience is required.
- Experience in physical design and timing closure for advanced nodes.
- Experience in Cadence EDA tools for physical design and verification.
- Experience in floor planning, power planning, CTS specification, place & route, and timing closure.
- Experience in UPF specs design and implementation.
- Be able to work with cross-functional teams, IP, and EDA vendors
Follow Cutshort