7+ RTL Jobs in India

1. Coding and Debugging in C language.
2. Knowledge on ARM based architectures of 8/16/32 Microcontrollers,UART, ADC, DAC,Ethernet, SPI,CAN,I2C and I2S.
3. FPGA RTL coding and Simulation using Verilog/VHDL

Qualification - BE/B.Tech (ECE), M.Sc.(Electronics)

Only Defense and Aerospace, Electronics, Semi-Conductors,

(No Automative industry)

AVANTEL LIMITED is a technology driven public limited company with focus on developing innovative wireless communication products and solutions to meet unique requirements of defense, railways, and telecom sectors. The organization is certified against AS 9100D and ISO 9001:2015 standards for Quality Management System. For more details visit www.avantel.in.

Job Description :

Own partition floorplanning for optimizing blocks for Power, Performance and Area.

Own execution from synthesis to place and route of partitions through all signoff including timing signoff, physical verification, EMIR signoff , Formal Equivalence, and Low Power Verification.

Have close collaboration with RTL team to help drive and resolve design issues related to block closure.

Understand tools, flows, and overall design methodology in design construction, signoff, and optimization with a data driven approach.

Implement robust clock distribution solutions using appropriate methods that meet design requirements.

Make good independent technical trade-offs between power, area, and timing (PPA)

Responsibilities will include, but are not limited to:

• Contribute to new Memory based product opportunities by assisting with the overall design, layout, and optimization of Memory/Logic circuits
• Responsible to translate system-level specs onto the circuit block-level performance spec, circuit architecture, design and development
• Perform verification processes with modeling and simulation using industry-standard simulators
• Document and review final results
• Chip in to cross-group communication to work towards standardization and group success
• Actively solicit guidance from Standards, CAD, modeling, and verification groups to ensure the design quality

Successful candidates for this position will have:

• A Bachelor's or Master's degree (Preferred) in Electrical Engineering, Computer Engineering, or related discipline
• Proven knowledge of CMOS Circuit Design
• Experience in RTL design, design synthesis, static timing analysis, and automated layout techniques
• Hands-on experience with Verilog modeling and simulation tools
• Knowledge of state machine logic/design verification techniques
• Excellent problem-solving and analytical skills
• Experience with a scripting language (Python, Tcl, Perl, etc)

• Work with the RTL and System design teams to drive the physical design of the device in the early design cycle.
• Design, implement and verify suitable methodology that meets the QoR goals.
• Resolve design and flow issues related to the physical design, identify potential solutions, and drive

• Deliver physical design of entire SoC, complete with specification, flow and automation.
• Interface with the RTL design team to drive design modifications to resolve physical design issues and

• Use EDA tool-based programming and scripting techniques to automate and improve throughput and quality.
• Interact with tool vendors to drive tool fixes and flow improvements. Perform tool evaluations of new

• Bachelor’s degree (Master’s preferred) in Electrical Engineering or comparable engineering discipline.
• 5 to 8 years of relevant experience is required.
• Experience in physical design and timing closure for advanced nodes.
• Experience in Cadence EDA tools for physical design and verification.
• Experience in floor planning, power planning, CTS specification, place & route, and timing closure.
• Experience in UPF specs design and implementation.
• Be able to work with cross-functional teams, IP, and EDA vendors

Job Description

We are looking for a Mobile and Javascript developer who is proficient with React Native, React.js, and Typescript with 2 years of experience. The primary focus will be on developing UI components with React Native and React JS workflows with Typescript. This will include the use of automated integration tests with RTL. These components are expected to be robust and easy to maintain with the highest code quality. The coordination with the rest of the team working on different layers of the infrastructure should be effective. 

Responsibilities

• • Delivering a complete mobile application OR front-end application using React Native/React JS and Typescript.
• • Building reusable components/widgets and front-end libraries for future use.
• • Translating designs and wireframes into high-quality code.
• • Writing tested, idiomatic, and documented code.
• • Optimizing components for maximum performance across multiple web browsers.
• • Mentoring junior developers, peer-to-peer code reviews, and ensuring that high.
• • Code quality bar should be maintained. Skills
• • Excellent proficiency in React Native, JavaScript, CSS, and HTML, including DOM manipulation and the JavaScript object model.
• • Thorough understanding of React Native, React JS, Typescript, and its core principles.
• • Experience with popular React Native andReact.js workflows (such as React-Redux, React-Router, React Hooks, etc.)
• • Experience with Class components and Functional components.
• • Experience with React Testing Library (RTL). Familiarity with Enzyme, Jest Framework and Cypress.
• • Experience with data structure libraries (e.g. Immutable.js)
• Experience with Backend technology like NodeJS, AWS
• • Familiarity with the front-end development tools such as Babel, Webpack, NPM, etc.
• • Experience with code versioning tools Git and its workflows.
• • Ability to solve problems effectively.
• • Ability to learn and explore new things effectively.
• • Familiarity with RESTful APIs.
• • Ability to understand business requirements and translate them into technical requirements.
• • Professional, precise communication skills.
• • Clear understanding of design patterns especially MV*.
• Experience with AWS is a big plus

Skills/Experience

Experience with complete flows involving timing closure of high speed digital design using scripting languages and design automation.

Has deep knowledge of Xilinx FPGA implementation and tools.

Experience in state of the art tools and flows.

Working knowledge in Verilog and System Verilog.

 Job Requirements

Bachelors in Electronics Engineering.

Strong knowledge of ASIC and/or FPGA design methodology and should be well versed in front-end design, simulation, and verification CAD tools.

Relevant FPGA/ASIC engineering design and verification experience is entertained.

Excellent verbal, written and communication skills are required.

Excellent follow-through, motivation, and persistence

Strong technical judgment and decision making abilities.

Knowledge of digital board design and signal integrity principles is a plus.