Own execution from synthesis to place and route of partitions through all signoff including timing signoff, physical verification, EMIR signoff , Formal Equivalence, and Low Power Verification.

Have close collaboration with RTL team to help drive and resolve design issues related to block closure.

Understand tools, flows, and overall design methodology in design construction, signoff, and optimization with a data driven approach.

Implement robust clock distribution solutions using appropriate methods that meet design requirements.

Make good independent technical trade-offs between power, area, and timing (PPA)

Job Description :

Own partition floorplanning for optimizing blocks for Power, Performance and Area.

Own execution from synthesis to place and route of partitions through all signoff including timing signoff, physical verification, EMIR signoff , Formal Equivalence, and Low Power Verification.

Have close collaboration with RTL team to help drive and resolve design issues related to block closure.

Understand tools, flows, and overall design methodology in design construction, signoff, and optimization with a data driven approach.

Implement robust clock distribution solutions using appropriate methods that meet design requirements.

Make good independent technical trade-offs between power, area, and timing (PPA)

Users love Cutshort

Read about what our users have to say about finding their next opportunity on Cutshort.

Subodh Popalwar

Software Engineer, Memorres

For 2 years, I had trouble finding a company with good work culture and a role that will help me grow in my career. Soon after I started using Cutshort, I had access to information about the work culture, compensation and what each company was clearly offering.

Companies hiring on Cutshort

About Samniya Techsys

Founded :

2017

Type

Size :

100-1000

Stage :

Bootstrapped

About

Samniya is a global technology company that provides expert solutions to customers in industries such as Aerospace, Automotive, Railways, Industrial Automation, and IT. With a team of experienced engineers in domains such as Structural/ component/Tools Engineering, Software Engineering, Embedded Engineering, Wire Harness Fabrication, Test Systems & Solutions, and Talent Management, Samniya offers end-to-end solutions and support to its customers worldwide. The company's global-friendly business process and methodology ensure cost-effective support and services to its local and global customers, fostering long-term mutually beneficial associations.

Company social profiles

N/A

Similar jobs

RTL Design Engineer

at Micron

Agency job

via GLOBAL TALENT EXC by Shriya Malpani

Hyderabad

10 - 20 yrs

₹5L - ₹10L / yr

RTL

Full chip

Responsibilities will include, but are not limited to:

Contribute to new Memory based product opportunities by assisting with the overall design, layout, and optimization of Memory/Logic circuits
Responsible to translate system-level specs onto the circuit block-level performance spec, circuit architecture, design and development
Perform verification processes with modeling and simulation using industry-standard simulators
Document and review final results
Chip in to cross-group communication to work towards standardization and group success
Actively solicit guidance from Standards, CAD, modeling, and verification groups to ensure the design quality

Successful candidates for this position will have:

A Bachelor's or Master's degree (Preferred) in Electrical Engineering, Computer Engineering, or related discipline
Proven knowledge of CMOS Circuit Design
Experience in RTL design, design synthesis, static timing analysis, and automated layout techniques
Hands-on experience with Verilog modeling and simulation tools
Knowledge of state machine logic/design verification techniques
Excellent problem-solving and analytical skills
Experience with a scripting language (Python, Tcl, Perl, etc)

Responsibilities will include, but are not limited to:

Contribute to new Memory based product opportunities by assisting with the overall design, layout, and optimization of Memory/Logic circuits
Responsible to translate system-level specs onto the circuit block-level performance spec, circuit architecture, design and development
Perform verification processes with modeling and simulation using industry-standard simulators
Document and review final results
Chip in to cross-group communication to work towards standardization and group success
Actively solicit guidance from Standards, CAD, modeling, and verification groups to ensure the design quality

Successful candidates for this position will have:

A Bachelor's or Master's degree (Preferred) in Electrical Engineering, Computer Engineering, or related discipline
Proven knowledge of CMOS Circuit Design
Experience in RTL design, design synthesis, static timing analysis, and automated layout techniques
Hands-on experience with Verilog modeling and simulation tools
Knowledge of state machine logic/design verification techniques
Excellent problem-solving and analytical skills
Experience with a scripting language (Python, Tcl, Perl, etc)

FPGA

at Jio Platforms Limited

3 recruiters

Agency job

via Skillathon by Abhijit Choudhary

Mumbai

2 - 7 yrs

₹6L - ₹9L / yr

FPGA

FGPA Developer

AXI

RTL

vivaldo

Job Description:
 FPGA Physical Layer Developer for 5G-NR
 Experience: 2 years to 6 years

Skill:
 FPGA IP Blocks integration using Xilinx Vivado Platform
 Knowledge on AXI Protocols
 Xilinx PS-PL integration knowledge
 RTL Programming: Verilog
 FPGA Test Bench Development using Xilinx Vivado
 L1/Physical Layer Implementation on Xilinx FPGA (RFSoC)
 FPGA Debugging Tools Experience: ILA, chipscope, VIO
 Working knowledge of the following engineering tools: Xilinx Vivado, Xilinx ISE/EDK
 FPGA Modem/Communication Blocks development/testing experience regarding 4G/5G
or any wireless standard will be preferred
 M.Tech. in VLSI will be preferred
 Good Academic Score

Senior Physical Design Engineer

at Innophase

1 video

Posted by Cheryl Lavya

Bengaluru (Bangalore)

5 - 10 yrs

₹10L - ₹40L / yr

Electrical engineering

RTL

Systems design

EDA

UPF

INNOPHASE is a rapidly growing pre-IPO communications semiconductor company with headquarters in San Diego, CA, and advanced design centers in Irvine, CA, San Jose, CA, Kista, Sweden, and Bangalore, India. We pioneered the industry’s lowest power Wi-Fi radio architecture for IoT applications and a revolutionary 5G platform that will transform cellular network deployments. Utilizing our breakthrough, patented, wireless technology we are bringing to market a portfolio of SoCs and modules with a unique value proposition for IoT and 5G applications.

InnoPhase Bangalore is looking for a Senior Engineer, Digital Physical Design to join a growing start

up semiconductor development organization and to help drive excellence in our IoT products.

Roles & Responsibilities

Design, Develop and execute physical design implementation of low-power and high-performance SoC, including

logic synthesis, floorplan and power plan, power domain specification, place and route, clock tree synthesis, static

timing analysis, IR drop analysis, EM, and physical verification in advanced technology nodes.

Work with the RTL and System design teams to drive the physical design of the device in the early design cycle.
Design, implement and verify suitable methodology that meets the QoR goals.
Resolve design and flow issues related to the physical design, identify potential solutions, and drive

execution.

Deliver physical design of entire SoC, complete with specification, flow and automation.
Interface with the RTL design team to drive design modifications to resolve physical design issues and

implement ECOs.

Use EDA tool-based programming and scripting techniques to automate and improve throughput and quality.
Interact with tool vendors to drive tool fixes and flow improvements. Perform tool evaluations of new

vendor tools and functions.

Desired Qualities

Bachelor’s degree (Master’s preferred) in Electrical Engineering or comparable engineering discipline.
5 to 8 years of relevant experience is required.
Experience in physical design and timing closure for advanced nodes.
Experience in Cadence EDA tools for physical design and verification.
Experience in floor planning, power planning, CTS specification, place & route, and timing closure.
Experience in UPF specs design and implementation.
Be able to work with cross-functional teams, IP, and EDA vendors

Work with the RTL and System design teams to drive the physical design of the device in the early design cycle.
Design, implement and verify suitable methodology that meets the QoR goals.
Resolve design and flow issues related to the physical design, identify potential solutions, and drive

execution.

Deliver physical design of entire SoC, complete with specification, flow and automation.
Interface with the RTL design team to drive design modifications to resolve physical design issues and

implement ECOs.

Use EDA tool-based programming and scripting techniques to automate and improve throughput and quality.
Interact with tool vendors to drive tool fixes and flow improvements. Perform tool evaluations of new

vendor tools and functions.

Desired Qualities

Bachelor’s degree (Master’s preferred) in Electrical Engineering or comparable engineering discipline.
5 to 8 years of relevant experience is required.
Experience in physical design and timing closure for advanced nodes.
Experience in Cadence EDA tools for physical design and verification.
Experience in floor planning, power planning, CTS specification, place & route, and timing closure.
Experience in UPF specs design and implementation.
Be able to work with cross-functional teams, IP, and EDA vendors

VLSI RTL Engineer

at Young Minds Technology Solutions Pvt Ltd

1 recruiter

Posted by Venkat Sai Narayan

Tirupati

0 - 2 yrs

₹1.2L - ₹3L / yr

Very Large Scale Integration (VLSI)

RTL

Verilog

Analog electronics

Application Specific Integrated Circuit (ASIC)

+1 more

Skills/Experience

Experience with complete flows involving timing closure of high speed digital design using scripting languages and design automation.

Has deep knowledge of Xilinx FPGA implementation and tools.

Experience in state of the art tools and flows.

Working knowledge in Verilog and System Verilog.

Job Requirements

Bachelors in Electronics Engineering.

Strong knowledge of ASIC and/or FPGA design methodology and should be well versed in front-end design, simulation, and verification CAD tools.

Relevant FPGA/ASIC engineering design and verification experience is entertained.

Excellent verbal, written and communication skills are required.

Excellent follow-through, motivation, and persistence

Strong technical judgment and decision making abilities.

Knowledge of digital board design and signal integrity principles is a plus.

Skills/Experience

Experience with complete flows involving timing closure of high speed digital design using scripting languages and design automation.

Has deep knowledge of Xilinx FPGA implementation and tools.

Experience in state of the art tools and flows.

Working knowledge in Verilog and System Verilog.

Job Requirements

Bachelors in Electronics Engineering.

Strong knowledge of ASIC and/or FPGA design methodology and should be well versed in front-end design, simulation, and verification CAD tools.

Relevant FPGA/ASIC engineering design and verification experience is entertained.

Excellent verbal, written and communication skills are required.

Excellent follow-through, motivation, and persistence

Strong technical judgment and decision making abilities.

Knowledge of digital board design and signal integrity principles is a plus.

ASIC VERIFICATION

at Swedium Global Services

2 recruiters

Posted by harshini talla

SWEDEN, FINLAND

5 - 12 yrs

₹15L - ₹30L / yr

Application Specific Integrated Circuit (ASIC)

VLSI

Verilog

UVM

+1 more

Job description: A strong experience in block design and IP verification within digital ASIC. Good experience in SystemVerilog and UVM Methodology based verification Minimum of 5+ Years of ASIC Verification experience Good command on English both in written and spoken, Swedish language knowledge is an advantage You should have Positive attitude, social skills, a desire to help team members, structured way of working and an eye for quality work. You enjoy working both independently and in a small diverse and you are focused on reaching result on time. The work will be carried out in a cross functional team using Scrum/Agile ways of working Skills Required: Design verification Skills Miscellaneous tasks in connection to the block design Verification planning Verification specification Verification environment (creation/adaptation/maintenance). Verification documentation Test case creation Usage of reference models Constrained random testing Creation of Coverage matrix Experienced in WCDMA, GSM and/or LTE systems.

Asic Verification Engineer

at Indium Global Services

Posted by VAISHAK A

Bengaluru (Bangalore)

5 - 7 yrs

₹10L - ₹20L / yr

VLSI

SOC

"IP"

"system verilog"

"UVM"

We are hiring Verification Engineers (DV) with good exposure to System Verilog and UVM methodologies. Work Location: Bangalore Experience: 5+ Years Job Description: 5+ Yrs Experience in Design Verification. Expertise in verifying complex designs from System as well as block level, through Design flow. Experience in building SV-UVM test Environment.

Why apply to jobs via Cutshort