Responsibilities will include, but are not limited to:
- Contribute to new Memory based product opportunities by assisting with the overall design, layout, and optimization of Memory/Logic circuits
- Responsible to translate system-level specs onto the circuit block-level performance spec, circuit architecture, design and development
- Perform verification processes with modeling and simulation using industry-standard simulators
- Document and review final results
- Chip in to cross-group communication to work towards standardization and group success
- Actively solicit guidance from Standards, CAD, modeling, and verification groups to ensure the design quality
Successful candidates for this position will have:
- A Bachelor's or Master's degree (Preferred) in Electrical Engineering, Computer Engineering, or related discipline
- Proven knowledge of CMOS Circuit Design
- Experience in RTL design, design synthesis, static timing analysis, and automated layout techniques
- Hands-on experience with Verilog modeling and simulation tools
- Knowledge of state machine logic/design verification techniques
- Excellent problem-solving and analytical skills
- Experience with a scripting language (Python, Tcl, Perl, etc)
About Micron
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Experience: 2 years to 6 years
Skill:
FPGA IP Blocks integration using Xilinx Vivado Platform
Knowledge on AXI Protocols
Xilinx PS-PL integration knowledge
RTL Programming: Verilog
FPGA Test Bench Development using Xilinx Vivado
L1/Physical Layer Implementation on Xilinx FPGA (RFSoC)
FPGA Debugging Tools Experience: ILA, chipscope, VIO
Working knowledge of the following engineering tools: Xilinx Vivado, Xilinx ISE/EDK
FPGA Modem/Communication Blocks development/testing experience regarding 4G/5G
or any wireless standard will be preferred
M.Tech. in VLSI will be preferred
Good Academic Score
Skills/Experience
Experience with complete flows involving timing closure of high speed digital design using scripting languages and design automation.
Has deep knowledge of Xilinx FPGA implementation and tools.
Experience in state of the art tools and flows.
Working knowledge in Verilog and System Verilog.
Job Requirements
Bachelors in Electronics Engineering.
Strong knowledge of ASIC and/or FPGA design methodology and should be well versed in front-end design, simulation, and verification CAD tools.
Relevant FPGA/ASIC engineering design and verification experience is entertained.
Excellent verbal, written and communication skills are required.
Excellent follow-through, motivation, and persistence
Strong technical judgment and decision making abilities.
Knowledge of digital board design and signal integrity principles is a plus.