FPGA Physical Layer Developer for 5G-NR
Experience: 2 years to 6 years
Skill:
FPGA IP Blocks integration using Xilinx Vivado Platform
Knowledge on AXI Protocols
Xilinx PS-PL integration knowledge
RTL Programming: Verilog
FPGA Test Bench Development using Xilinx Vivado
L1/Physical Layer Implementation on Xilinx FPGA (RFSoC)
FPGA Debugging Tools Experience: ILA, chipscope, VIO
Working knowledge of the following engineering tools: Xilinx Vivado, Xilinx ISE/EDK
FPGA Modem/Communication Blocks development/testing experience regarding 4G/5G
or any wireless standard will be preferred
M.Tech. in VLSI will be preferred
Good Academic Score

About Jio Platforms Limited
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