FPGA Physical Layer Developer for 5G-NR
Experience: 2 years to 6 years
Skill:
FPGA IP Blocks integration using Xilinx Vivado Platform
Knowledge on AXI Protocols
Xilinx PS-PL integration knowledge
RTL Programming: Verilog
FPGA Test Bench Development using Xilinx Vivado
L1/Physical Layer Implementation on Xilinx FPGA (RFSoC)
FPGA Debugging Tools Experience: ILA, chipscope, VIO
Working knowledge of the following engineering tools: Xilinx Vivado, Xilinx ISE/EDK
FPGA Modem/Communication Blocks development/testing experience regarding 4G/5G
or any wireless standard will be preferred
M.Tech. in VLSI will be preferred
Good Academic Score
Similar jobs
1.SV, UVM, USB, DDR, PCIE, Ethernet, Axi, MIPI. Any one of the protocols will
be added advantage.
2.Experience in verification of complex IPs or SoCs.
3. Expertise in SoC Verification using C and SV/UVM.Expertise in AMBA
protocols
4. AXI/AHB/APB and experience in working with ARM Processors.
5. Expertise in Test Plan creation and Verification technologies like Code
Coverage, Functional Coverage and Assertions.
Required Skillset:
- Understands multi-threading and has decent level knowledge of multi-core architectures.
- Technically proficient and hands-on in C++ with a good understanding of C++11 and C++14.
- Knowledge of TCP/IP, UDP & Network topology. Passionate to debug network problems with proficiency in-network and socket programming.
- Ideally should have worked on User space networking stack like Solarflare, Melanox etc.
- Should be able to get hands dirty on things like ASAN, SystemTAP, tcpdump, gdb. etc.
- Should love working on Linux, its kernel and optionally is be aware of Linux optimizations pertaining to low latency.
- Experience of working in HFT (understands order books, strategies etc.) and keen to keep reducing latency, erasing jitter, identify and eliminate queue buildup/congestion in the system.
Desired Skills :
- Passionate about coding and a fast learner.
- Hardware and FPGA work experience a big plus.
- Has worked on Solarflare, Exablaze, etc.
- Ability to work as a team player as well as an individual contributor.
Benefits :
We work hard. Period. :)
We also value the quality of life. Our cubicle free workplace and informally clad workforce reflect this. Benefits include:
- Competitive salary
- Few weeks of paid vacation
- Interaction and collaboration with global experts
- Annual out-station offsite(s) and frequent outings
- Multiple performance-based bonuses
- Health insurance
- A fun work environment with dedicated sports and recreation facilities.
- Opportunities to learn and lead: Frequent Knowledge Sharing Sessions conducted by co-workers
- Work-related and extra-curricular competitions at the office
Skills/Experience
Experience with complete flows involving timing closure of high speed digital design using scripting languages and design automation.
Has deep knowledge of Xilinx FPGA implementation and tools.
Experience in state of the art tools and flows.
Working knowledge in Verilog and System Verilog.
Job Requirements
Bachelors in Electronics Engineering.
Strong knowledge of ASIC and/or FPGA design methodology and should be well versed in front-end design, simulation, and verification CAD tools.
Relevant FPGA/ASIC engineering design and verification experience is entertained.
Excellent verbal, written and communication skills are required.
Excellent follow-through, motivation, and persistence
Strong technical judgment and decision making abilities.
Knowledge of digital board design and signal integrity principles is a plus.