Skills/Experience
Experience with complete flows involving timing closure of high speed digital design using scripting languages and design automation.
Has deep knowledge of Xilinx FPGA implementation and tools.
Experience in state of the art tools and flows.
Working knowledge in Verilog and System Verilog.
Job Requirements
Bachelors in Electronics Engineering.
Strong knowledge of ASIC and/or FPGA design methodology and should be well versed in front-end design, simulation, and verification CAD tools.
Relevant FPGA/ASIC engineering design and verification experience is entertained.
Excellent verbal, written and communication skills are required.
Excellent follow-through, motivation, and persistence
Strong technical judgment and decision making abilities.
Knowledge of digital board design and signal integrity principles is a plus.
Subodh Popalwar
Software Engineer, Memorres
About Young Minds Technology Solutions Pvt Ltd
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Responsibilities will include, but are not limited to:
- Contribute to new Memory based product opportunities by assisting with the overall design, layout, and optimization of Memory/Logic circuits
- Responsible to translate system-level specs onto the circuit block-level performance spec, circuit architecture, design and development
- Perform verification processes with modeling and simulation using industry-standard simulators
- Document and review final results
- Chip in to cross-group communication to work towards standardization and group success
- Actively solicit guidance from Standards, CAD, modeling, and verification groups to ensure the design quality
Successful candidates for this position will have:
- A Bachelor's or Master's degree (Preferred) in Electrical Engineering, Computer Engineering, or related discipline
- Proven knowledge of CMOS Circuit Design
- Experience in RTL design, design synthesis, static timing analysis, and automated layout techniques
- Hands-on experience with Verilog modeling and simulation tools
- Knowledge of state machine logic/design verification techniques
- Excellent problem-solving and analytical skills
- Experience with a scripting language (Python, Tcl, Perl, etc)
Responsibilities
- Responsible for design and spec development and design of analog blocks for advanced mixed-signal / analog circuits.
- Write detailed design specification and will be in close collaboration with the system architect, circuit designers and design verification engineers.
- Work on behavioral modeling of analog blocks and support design verification to ensure bug free silicon.
- Lead development of analog blocks in collaboration with external vendors and lead integration, test plan and characterization efforts.
Requirements
- Strong track record of architect, develop, verification and validation of complete silicon IPs
- Deep understanding of bandgaps, bias, opamps, switched-cap circuits, LDOs, PLLs, feedback and compensation techniques, DCDC converters
- In-depth knowledge and good understanding of analog design techniques.
- Experience in digital integration of analog IPs with chip level integration team
- Experience in developing behavior modeling a plus
- Experience IP design management or vendor management a plus
- Strong device physics knowledge as it applies to analog IC design
- Hand-on experience with IP lab characterization using spectrum analyzers, oscilloscopes, signal generators, etc.
- Experience in working with production test engineers to produce test plans and design for testability details
- Excellent communication skills
- Team player with an ability to encourage team members
Education & Experience
- MS (preferred in EE) plus 8 years
- PhD (preferred in EE) plus 5 years
Note:
Annual job salary: The annual job salary mentioned in this posting is a default number taken by cutshort and is inaccurate. <Not mentioned/ disclosed by Rivos>
Resumes:
Interested folks with 3+ years to 20 years of experience into AMS Design, Please reach out to the Recruiter Deepa Savant to learn more about the job and discuss details.
Custom Memory Design
SRAM/custom circuit design and standard cell design
|
Qualifications • Candidates must have 7+ years of experience in transistor level custom circuit design from RTL-GDS for CPU and SoC, circuit simulation, equivalence checking, PPA trade off analysis, low power design techniques, timing, noise and power characterization • Prior experience and proven success of successfully designing high performance SRAM memories, Register file memories, SRAM compilers, data path designs and standard cells • Experience designing transistor-level custom circuits in advanced FinFET technology nodes • Solid understanding of device physics, process technology and circuit design techniques for high performance, low power • Experience with advanced process design rules and supervising mask design • Knowledge developing automation for compilers and standard cells • Post-Silicon test and debug experience • Ability to work well in a team and be productive under aggressive schedules • Excellent problem solving, written and verbal communication • Master's Degree or Bachelor's Degree with 7+ years of experience |
Responsibilities • The role will be at the center of a state-of-the-art circuit design effort, interfacing with all disciplines and have a critical impact on getting products to market quickly • Responsible for designing and delivering custom circuits from scratch • Drive design and development of SRAM, register file, custom cells to enable high performance and low power designs • Work with microarchitecture team to gather specifications • Drive optimal implementation Conduct early sizing estimates and PPA analysis • Perform design entry and simulations for optimal design sizing • Work closely with mask designers on custom design implementation, DFM and yield enhancement features • Collaborate with the CPU and SoC Physical design teams on floorplanning, placement, timing and power closure of the custom design • Interact with technology team • Participate in developing design and test plans Collaborate with the CAD team and drive design flow enhancements |
Job description
Rivos Custom Circuits team is seeking highly motivated candidates to develop state of the art custom SRAM memories, Register file memories, memory compilers and standard cells to improve circuit performance, optimize dynamic and static power and support silicon bring up. The role will be at the center of a state-of-the-art circuit design effort, interfacing with all disciplines and have a critical impact on getting products to market quickly.
Responsibilities
- Responsible for designing and delivering custom circuits from scratch.
- Drive design and development of SRAM, register file, custom cells to enable high performance and low power designsWork with microarchitecture team to gather specifications
- Drive optimal implementation Conduct early sizing estimates and PPA analysis. Perform design entry and simulations for optimal design sizingWork closely with mask designers on custom design implementation, DFM and yield enhancement featuresCollaborate with the CPU and SoC Physical design teams on floorplanning, placement, timing and power closure of the custom designInteract with technology team
- Participate in developing design and test plans Collaborate with the CAD team and drive design flow enhancements
Qualification
- Candidates must have 7+ years of experience in transistor level custom circuit design from RTL-GDS for CPU and SoC, circuit simulation, equivalence checking, PPA trade off analysis, low power design techniques, timing, noise and power characterization.
- Prior experience and proven success of successfully designing high performance SRAM memories, Register file memories, SRAM compilers, data path designs and standard cells
- Experience designing transistor-level custom circuits in advanced FinFET technology nodes
- Solid understanding of device physics, process technology and circuit design techniques for high performance, low power
- Experience with advanced process design rules and supervising mask design
- Knowledge developing automation for compilers and standard cells
- Post-Silicon test and debug experience
- Ability to work well in a team and be productive under aggressive schedules.
- Excellent problem solving, written and verbal communication
Education and Experience
- Master's Degree or Bachelor's Degree with 7+ years of experience
FPGA Physical Layer Developer for 5G-NR
Experience: 2 years to 6 years
Skill:
FPGA IP Blocks integration using Xilinx Vivado Platform
Knowledge on AXI Protocols
Xilinx PS-PL integration knowledge
RTL Programming: Verilog
FPGA Test Bench Development using Xilinx Vivado
L1/Physical Layer Implementation on Xilinx FPGA (RFSoC)
FPGA Debugging Tools Experience: ILA, chipscope, VIO
Working knowledge of the following engineering tools: Xilinx Vivado, Xilinx ISE/EDK
FPGA Modem/Communication Blocks development/testing experience regarding 4G/5G
or any wireless standard will be preferred
M.Tech. in VLSI will be preferred
Good Academic Score
alog Circuit Design::
- The candidate should have B.Tech or M.Tech in Electronics/Electrical/VLSI Design Engineering
- The candidate should have relevant work experience of 7-16 years in Analog and SERDES IO IP design e.g. GPIOs, Thermal Sensor, PLL, ADC/DAC/ Voltage regulators/LDOs, AIB, HBMIO, DDR, HDMI/DP IO, MIPI IO etc.
Physical Design - JD
Experience: 2-20 yrs
1.Strong background of ASIC Physical Design: Floor planning, P&R, Extraction, IR Drop Analysis, Static Timing and Signal Integrity.
2.Hands-on experience on technology nodes like 7nm, 14nm, 10nm.
3.Good knowledge of EDA tools from Synopsys , Cadence and Mentor
4.Hands-on experience in floor planning, placement optimizations, CTS and routing.
5.Hands-on experience in cadence or Synopsys tool (Encounter, ICC, PT/PTSI, TEMPUS, DC, RC, VOLTAS)
1.SV, UVM, USB, DDR, PCIE, Ethernet, Axi, MIPI. Any one of the protocols will
be added advantage.
2.Experience in verification of complex IPs or SoCs.
3. Expertise in SoC Verification using C and SV/UVM.Expertise in AMBA
protocols
4. AXI/AHB/APB and experience in working with ARM Processors.
5. Expertise in Test Plan creation and Verification technologies like Code
Coverage, Functional Coverage and Assertions.
Dear Connections,
Roles & Responsibility:-
Should execute block level floor planning, PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks.
Physical Design Implementation on advanced technology nodes like 28nm, 20nm for block level implementation. Good understanding on low power concepts. Good understanding on top level physical design, partitioning and timing constraints, IR Drop.
Candidate should be from semiconductor/'ASIC industry
Excellent knowledge on GDS To Netlift
Follow CutshortSubodh Popalwar
Software Engineer, Memorres