GLOBAL TALENT EXC

Responsibilities will include, but are not limited to:

• Contribute to new Memory based product opportunities by assisting with the overall design, layout, and optimization of Memory/Logic circuits
• Responsible to translate system-level specs onto the circuit block-level performance spec, circuit architecture, design and development
• Perform verification processes with modeling and simulation using industry-standard simulators
• Document and review final results
• Chip in to cross-group communication to work towards standardization and group success
• Actively solicit guidance from Standards, CAD, modeling, and verification groups to ensure the design quality

Successful candidates for this position will have:

• A Bachelor's or Master's degree (Preferred) in Electrical Engineering, Computer Engineering, or related discipline
• Proven knowledge of CMOS Circuit Design
• Experience in RTL design, design synthesis, static timing analysis, and automated layout techniques
• Hands-on experience with Verilog modeling and simulation tools
• Knowledge of state machine logic/design verification techniques
• Excellent problem-solving and analytical skills
• Experience with a scripting language (Python, Tcl, Perl, etc)

Responsibilities

• Provide leadership in building and growing a Custom layout team from the ground up to support the global DRAM layout requirement;
• Provide leadership in developing Analog and custom layouts to meet schedules and milestones;
• Provide leadership in training the team’s technical skills and cultural healthiness.
• Effectively communicating with engineering teams across multiple countries to ensure the success of the layout project.
• Organize, prioritize, and manage logistics on tasks and resource allocations for multiple projects.
• Manage the performance and development of team members.
• Managing hiring and retention.
• As a critical member of the core DRAM leadership team in India, contributed to the overall success

Qualification/Requirements

• 5 + year experience in analog/custom layout in advanced CMOS process.
• Minimum 3+ years people management experience.
• Expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS is a must.
• Must have strong skills in layout and floor planning skills and manual routing.
• Strong ability to build, and continuously develop a premier analog/mixed-signal layout team
• Experienced in managing multiple Custom IC layout projects
• Highly motivated with passion, detail-oriented, systematic, and methodical approach in IC layout design.
• The ability to work and communicate effectively in a team and to be able to multi-task effectively in a fast-paced working environment.
• Excellent verbal and written communication skills required.
• Independent with strong analytical skills, creative thinking and self-motivation.
• Capable of working in a cross-functional, multi-site team environment in multiple time zones.
• Previous work experience in DRAM/NAND layout design is desirable however not mandatory.

Responsibilities

 Develop an effective test suite based on the FPGA requirements.

 Testbench architecture with System Verilog and UVM

 Develop test environments based on the architecture.

 Develop Agents, Drivers, Monitors, Predictors, Scoreboard, and Sequences etc.

 Actively participate in a team environment, working with verification,

architecture, applications, and design teams to develop comprehensive

verification plans and address issues.

 Verification environment development/update for block level and system level.

 Own and drive verification related activities, provide technical support, and

proactively manage tasks to meet schedule goals.

 Define and develop effective functional assertions and coverpoints

 Debug the design issues and report through appropriate tools

 Code Coverage analysis and test case identification for improving the code

coverage.

 Perform timing simulations.

 Apply techniques and skills required to identify a root cause of a given issue and

very good debugging skills.

 Technical guidance to the junior engineers on verification tasks.

Qualifications

 Bachelor's/Master's degree in Engineering (Electronics and Communication or

VLSI )

 10+ years of Industry experience in development, integration & verification of

ASIC/FPGA.

 Protocols – PCIe, SPI, ARINC 429, Mil 1553, Image processing or similar.

 Hands on experience in developing System Verilog/UVM verification

environment from scratch.

 Hands on experience with Questa or similar advanced simulation tools.

 Hands on experience in DO-254 verification process.

 Experience in DOORS/Jama will be a plus.

 Experience in Video domain will be a plus.