4+ JTAG Jobs in India

Job Summary:

 We are looking for an experienced Embedded Software Developer with expertise in IEC 61850-based communication systems for embedded devices. The ideal candidate should have strong experience in Embedded C development, RTOS-based applications, and substation automation standards. The role involves developing, integrating, and maintaining embedded software solutions supporting IEC 61850 protocols while ensuring reliability, performance, and compliance with industry standards. 

Key Responsibilities 

● Develop embedded firmware using C and Embedded C for IEC 61850-enabled devices.

● Implement and maintain IEC 61850 communication stacks and data models. 

● Work with Logical Nodes (LN), Data Objects (DO), and Data Attributes (DA) as defined in IEC 61850. 

● Develop and validate SCL configuration files, including ICD, CID, and SCD files. 

● Develop networking applications using Ethernet and TCP/IP protocols. 

● Develop and maintain RTOS-based embedded applications using FreeRTOS or equivalent. ● Debug embedded applications using JTAG and SWD debugging tools. 

● Collaborate with hardware, firmware, and testing teams throughout the development lifecycle. 

● Perform code reviews, troubleshooting, and performance optimization. 

● Prepare technical documentation and support system integration activities. 

Required Skills 

● 5–7 years of experience in Embedded Firmware Development. 

● Minimum 1 year of hands-on experience with IEC 61850. 

● Strong programming skills in C and Embedded C. 

● Experience with RTOS concepts such as FreeRTOS or similar. 

● Experience debugging embedded systems using JTAG and SWD. 

● Strong understanding of the IEC 61850 data model, including Logical Nodes (LN), Data Objects (DO), and Data Attributes (DA). 

● Experience working with SCL files, including ICD, CID, and SCD. 

● Strong knowledge of Ethernet and TCP/IP networking. 

● Strong analytical, debugging, and problem-solving skills. 

● Willingness to work from Goa. 

Preferred Skills 

● Experience with substation automation systems and Intelligent Electronic Devices (IEDs). 

● Knowledge of power system communication protocols. 

● Experience with secure embedded software development practices. 

● Immediate joiners or candidates with a notice period of one month or less are preferred. 

Education Bachelor’s or Master’s degree in Electronics, Electrical Engineering, Embedded Systems, Computer Science, Computer Engineering, or a related field. 

Job Description:

We are looking for skilled Design for Test (DFT) Engineers with 3–8 years of experience to join our growing team. The ideal candidate should have strong expertise in DFT architecture, implementation, and validation for complex SoCs.

Key Responsibilities:

• Develop and implement DFT architectures (Scan, MBIST, LBIST, Boundary Scan)
• Work on scan insertion, ATPG pattern generation, and fault coverage analysis
• Collaborate with design and verification teams for testability improvements
• Perform DFT verification and debug of test patterns
• Handle silicon bring-up, debug, and yield improvement activities
• Ensure high-quality test coverage and optimize test time

Required Skills:

• Strong hands-on experience in Scan, ATPG, MBIST, LBIST
• Good knowledge of DFT tools like Tessent / Modus / Encounter Test
• Experience in JTAG / Boundary Scan (IEEE 1149.1)
• Understanding of SoC architecture and digital design concepts
• Scripting knowledge in Perl / Python / Tcl
• Experience in debugging silicon issues is a plus

Key Responsibilities

1. Kernel Lifecycle & Maintenance

Upstream Alignment: Lead the strategy for upgrading enterprise kernels (e.g., migrating from LTS 5.15 to 6.6) while maintaining binary compatibility where required.

Patch Porting: Expertly port functional and performance patches between disparate kernel versions, resolving complex code conflicts and API changes.

CVE Mitigation: Monitor the Linux Kernel Mailing List (LKML) and security advisories to identify and backport CVE patches from upstream to production environments.

2. Deep-Dive Debugging & Stability

Panic Analysis: Act as the final escalation point for Kernel Panics and "Oops" messages. Utilize kdump, crash, and gdb to perform post-mortem analysis of vmcores.

Boot-Time Resolution: Debug critical failures during the early boot process (UEFI handoff, initramfs, and early kernel init) where standard logging is unavailable.

Performance Tuning: Use ebpf, ftrace, and perf to identify bottlenecks in memory management, scheduler latency, or I/O throughput.

3. Driver Development & Hardware Integration

Driver Ownership: Design, develop, or maintain at least one Open Source or Proprietary Device Driver (Network, Storage, GPU, or Character devices).

Hardware Abstraction: Interface directly with hardware registers, managing DMA mappings, and optimizing interrupt handling (MSI-X, Threaded IRQs).

Out-of-Tree Management: Maintain driver compatibility across kernel updates using DKMS or similar frameworks.

4. Infrastructure & Automation

Registry Management: Oversee the distribution of custom kernel builds and modules via GitLab Container/Package Registries.

CI/CD for Kernel: Build automated testing pipelines (Hardware-in-the-loop) to validate kernel stability before enterprise-wide deployment.

Required Technical Skills:

Languages: Mastery of C/C++ Programming (C is preferred)

Kernel Internals: Deep understanding of VFS, Memory Management (MMU/Paging), Process Scheduling, and Networking Stacks.

Debugging Tools: Expert-level use of kprobes, trace-cmd, valgrind, and hardware-level debuggers (JTAG/Serial Console).

Build Systems: Proficiency with Kbuild, Makefiles, and building RPM/Debian packages for kernel distribution.

Security: Hands-on experience with SELinux/AppArmor policy development and kernel hardening (FIPS, KSPP).

1. Experience in JTAG, MBIST , Scan Compression, ATPG, Fault Simulation.
2. Experience with industry ATPG tools Synopsys Tetra MAX, Cadence Encounter Test or
3. Mentor Fast Scan ATPG tools Synopsys DFT scan insertion.
4. Experience with industry simulation tools such as VCS, ModelSim, NC Verilog etc.
5. Pattern Simulation with and without timing annotation & debugging