3 ATPG Jobs in Bangalore (Bengaluru) | ATPG Job openings in Bangalore (Bengaluru)

Hello Everyone

ElevarSoC hiring for Bangalore, Hyderabad locations

3-6 years of experience with Good DFT concepts in SCAN INSERTION, ATPG and Simulations.

Good exposure to Synth, ATPG tools (Mentor) : DRC & coverage analysis, Timing/no timing (VCS) simulations.

Anyone already worked for Qcomm/product company is preferable.

Candidate should be independent in handling the given task.

Mandatory Skills:

ATPG trace (DRC), Stuck at and TDF Coverage Analysis

ATPG no timing and timing vector simulations

Apply now!!

Job Description:

We are looking for skilled Design for Test (DFT) Engineers with 3–8 years of experience to join our growing team. The ideal candidate should have strong expertise in DFT architecture, implementation, and validation for complex SoCs.

Key Responsibilities:

• Develop and implement DFT architectures (Scan, MBIST, LBIST, Boundary Scan)
• Work on scan insertion, ATPG pattern generation, and fault coverage analysis
• Collaborate with design and verification teams for testability improvements
• Perform DFT verification and debug of test patterns
• Handle silicon bring-up, debug, and yield improvement activities
• Ensure high-quality test coverage and optimize test time

Required Skills:

• Strong hands-on experience in Scan, ATPG, MBIST, LBIST
• Good knowledge of DFT tools like Tessent / Modus / Encounter Test
• Experience in JTAG / Boundary Scan (IEEE 1149.1)
• Understanding of SoC architecture and digital design concepts
• Scripting knowledge in Perl / Python / Tcl
• Experience in debugging silicon issues is a plus

1. Experience in JTAG, MBIST , Scan Compression, ATPG, Fault Simulation.
2. Experience with industry ATPG tools Synopsys Tetra MAX, Cadence Encounter Test or
3. Mentor Fast Scan ATPG tools Synopsys DFT scan insertion.
4. Experience with industry simulation tools such as VCS, ModelSim, NC Verilog etc.
5. Pattern Simulation with and without timing annotation & debugging