Join a well funded startup as an analog engineer leading the designs for droop sensing, clocking, PLL, LDO, On-die VRs and PMICs using latest finfet technology nodes. Our mission is to reimagine silicon and disrupt the high performance computing platforms with the RiscV based chiplet designs.

Responsibilities

Responsible for design and spec development and design of analog blocks for advanced mixed-signal / analog circuits.
Write detailed design specification and will be in close collaboration with the system architect, circuit designers and design verification engineers.
Work on behavioral modeling of analog blocks and support design verification to ensure bug free silicon.
Lead development of analog blocks in collaboration with external vendors and lead integration, test plan and characterization efforts.

Requirements

Strong track record of architect, develop, verification and validation of complete silicon IPs
Deep understanding of bandgaps, bias, opamps, switched-cap circuits, LDOs, PLLs, feedback and compensation techniques, DCDC converters
In-depth knowledge and good understanding of analog design techniques.
Experience in digital integration of analog IPs with chip level integration team
Experience in developing behavior modeling a plus
Experience IP design management or vendor management a plus
Strong device physics knowledge as it applies to analog IC design
Hand-on experience with IP lab characterization using spectrum analyzers, oscilloscopes, signal generators, etc.
Experience in working with production test engineers to produce test plans and design for testability details
Excellent communication skills
Team player with an ability to encourage team members

Education & Experience

MS (preferred in EE) plus 8 years
PhD (preferred in EE) plus 5 years

Note:
Annual job salary: The annual job salary mentioned in this posting is a default number taken by cutshort and is inaccurate. <Not mentioned/ disclosed by Rivos>

Resumes:
Interested folks with 3+ years to 20 years of experience into AMS Design, Please reach out to the Recruiter Deepa Savant to learn more about the job and discuss details.

(INDIA) BANGALORE, INDIA /

ENGINEERING – SILICON ENGINEERING /

FULL-TIME

Responsibilities

Responsible for design and spec development and design of analog blocks for advanced mixed-signal / analog circuits.
Write detailed design specification and will be in close collaboration with the system architect, circuit designers and design verification engineers.
Work on behavioral modeling of analog blocks and support design verification to ensure bug free silicon.
Lead development of analog blocks in collaboration with external vendors and lead integration, test plan and characterization efforts.

Requirements

Strong track record of architect, develop, verification and validation of complete silicon IPs
Deep understanding of bandgaps, bias, opamps, switched-cap circuits, LDOs, PLLs, feedback and compensation techniques, DCDC converters
In-depth knowledge and good understanding of analog design techniques.
Experience in digital integration of analog IPs with chip level integration team
Experience in developing behavior modeling a plus
Experience IP design management or vendor management a plus
Strong device physics knowledge as it applies to analog IC design
Hand-on experience with IP lab characterization using spectrum analyzers, oscilloscopes, signal generators, etc.
Experience in working with production test engineers to produce test plans and design for testability details
Excellent communication skills
Team player with an ability to encourage team members

Education & Experience

MS (preferred in EE) plus 8 years
PhD (preferred in EE) plus 5 years

VLSI RTL Engineer

at Young Minds Technology Solutions Pvt Ltd

1 recruiter

Posted by Venkat Sai Narayan

Tirupati

0 - 2 yrs

₹1.2L - ₹3L / yr

Very Large Scale Integration (VLSI)

RTL

Verilog

Analog electronics

Application Specific Integrated Circuit (ASIC)

+1 more

Skills/Experience

Experience with complete flows involving timing closure of high speed digital design using scripting languages and design automation.

Has deep knowledge of Xilinx FPGA implementation and tools.

Experience in state of the art tools and flows.

Working knowledge in Verilog and System Verilog.

Job Requirements

Bachelors in Electronics Engineering.

Strong knowledge of ASIC and/or FPGA design methodology and should be well versed in front-end design, simulation, and verification CAD tools.

Relevant FPGA/ASIC engineering design and verification experience is entertained.

Excellent verbal, written and communication skills are required.

Excellent follow-through, motivation, and persistence

Strong technical judgment and decision making abilities.

Knowledge of digital board design and signal integrity principles is a plus.