Responsibilities
• End-to-End Embedded/DSP system design.
• Complex logic implementation using RTL coding techniques (preferably VHDL and HLS)
• Able to implement various complex algorithms and curve fitting/Neural network based algorithms inside the FPGA hardware.
• Writing modular RTL codes and design techniques using IPs.
• Simulating the design at various stages of development.
• CDC, STA, area/power optimizations, floor planning, linting.
• Interfacing high speed ADCs/DACs using state of the art data transfer links to FPGA.
• Using DDR RAM and SG-DMA for low latency, high-speed data transfer.
• Familiarity with high-speed communication systems viz. USB 3, PCIe, Gbe, 10 Gbe, 100
Gbe etc.
• Linux device driver development.
Skills
• VHDL/Verilog, C/C++, familiar with Xilinx development tools.
• Design knowledge of PCIe, LVDS, SPI, AXI, USB etc. interfaces.
• Ability to design using primitives instead of inferred design from RTL.
• Embedded linux device drivers, petalinux, exposure to yocto project.
• Exposure to various compression algorithms.
Desired Qualification/Experience
• Talent and zeal to work with new challenging system designs.
• Thorough understanding of digital systems.
• Hands-on experience on the RTL design, preferably with a repository of previous
projects
Subodh Popalwar
Software Engineer, Memorres
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Software Engineer, Memorres