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Do you want to own the PMIC, PLL, and PCIe buffer architectures that ship in millions of vehicles? Do you want to build and lead the team solving India's toughest automotive power and clocking challenges?

Role: Head of Engineering

Level Five Cartronics | Fabless Automotive Semiconductor Design

Location: MG Road, Bengaluru, Karnataka, India (On-site)

About Us

Founded by serial Entrepreneurs, Level Five Cartronics is a fabless semiconductor design company headquartered in Bengaluru, building automotive-grade Power Management ICs (PMICs), high-precision oscillators, and high-performance phase-locked loops (PLLs) for the next generation of vehicle electronics. Our portfolio centres on low-EMI power delivery — including spread-spectrum EMI suppression — and low-jitter clocking and interface solutions for safety-critical solutions and infotainment systems. We design DC-DC converters, LDOs, and clock distribution networks (including low-jitter PCIe Gen 4, 5, and 6 buffers) in CMOS and BCD high-voltage processes across the 55nm, 90nm and 180nm nodes. We own our products end to end, from architecture through silicon characterization and productization, as part of India's growing fabless semiconductor ecosystem.

The Role

We are looking for a hands-on Head of Engineering, based at our Bengaluru headquarters, to lead our analog/mixed-signal design organization. This is a senior leadership position for an engineer who has personally taken complex automotive power, clocking, and high-speed interface products from concept to high-volume production — and who can build, mentor, and scale the cross-functional team that does it again and again.

You will set the technical direction for our PMIC, oscillator, PLL, and PCIe buffer roadmaps, own design quality and tape-out readiness, and partner closely with characterization, product, and test engineering to ensure every product meets stringent automotive reliability, jitter, and EMC requirements.

What You'll Do

1. Lead and grow the analog/mixed-signal design, layout, and verification teams across multiple product lines, based out of our Bengaluru engineering center.

2. Own the technical architecture and execution of automotive-grade PMICs, DC-DC converters, LDOs, low phase noise Fractional-N phase-locked loops (PLLs), and low-jitter PCIe Gen 4, 5, and 6 buffers.

3. Target high-speed interface applications by driving low phase noise PLL architectures explicitly optimized for PCIe Gen 4, 5, and 6 standards.

4. Drive designs across CMOS and BCD high-voltage processes at 55nm, 90nm and 180nm, from specification through tape-out and qualification.

5. Set and enforce design methodology, review gates, and tape-out criteria; review schematics, layout, and verification plans personally where it matters.

6. Partner with characterization engineers on lab bring-up, silicon debug, and correlation of measured results to simulation.

7. Work side by side with product engineers on productization, test development, yield, and sustaining.

8. Build and lead cross-functional teams; recruit, develop, and retain top analog and layout talent in India's semiconductor talent market.

9. Be a technical authority and final escalation point for difficult design and silicon issues.

What You'll Bring

- Minimum of 12 years (preferably more) of experience in analog/mixed-signal design, layout, and productization.

- Demonstrated track record of taped-out databases and shipping full products in volume, not just isolated blocks.

- Deep expertise across the full flow: schematic design, layout, and lab characterization (understanding how each one constrains the others).

- Hands-on design of DC-DC converters and LDOs in CMOS and BCD high-voltage processes.

- Expertise in clocking and interfaces: deep understanding of low phase noise design, Fractional-N PLL architectures, and low-jitter PCIe Gen 4, 5, and 6 clock buffers/drivers.

- Experience with PMICs, oscillators, and spread-spectrum / EMI suppression techniques.

- Strong working knowledge of the 55nm, 90nm and 180nm process nodes.

- Extensive experience with Cadence EDA tools across the design and verification flow.

- Mixed-signal behavioral modeling in Verilog (Verilog/Verilog-AMS).

- Proven history of working closely with characterization and product engineers through bring-up and ramp.

- Demonstrated success building, leading, and recruiting cross-functional engineering teams.

Nice to Have

- Automotive qualification experience (AEC-Q100, ISO 26262 / functional safety awareness).

- Strong EMC/EMI design and measurement background.

- Experience scaling an engineering organization in a fabless environment, ideally within India's semiconductor ecosystem.

Why Level Five Cartronics

You'll own real products in a fast-moving automotive market, work across the full design-to-silicon flow, and shape the engineering culture of a growing fabless company based in Bengaluru — one of India's leading semiconductor design hubs. If you've built power, clocking, and high-speed interface products that ship in cars and you want to lead the team that builds the next ones, we'd like to talk.

Level Five Cartronics is an equal opportunity employer.

We are seeking a highly skilled and passionate Hardware Emulation Engineer to join our team working withthe best in the Industry, developing innovative ASIC solutions for data center and AI Infrastructure. As an Hardware Emulation Engineer, you will be at the forefront of pre-silicon validation, ensuring the highest quality and functionality of our hardware before it goes into production.

Key Responsibilities:

·      Emulation Environment Development: Build and maintain pre-silicon emulation platforms using industry-standard systems such as Cadence Palladium or Synopsys ZeBu or Veloce Strato, Primo

·      Model Integration and Optimization: Integrate the RTL design onto the emulation platform by ensuring synthesizability, optimize build efficiency and performance, and work with high-performance transactors and emulation testbenches (e.g., using SystemVerilog, C/C++, Python).

·      Flush out emulation flow issues by performing smoke verification

·      Support validation team in execute comprehensive test content, including bare-metal and OS-based tests, to accelerate bug finding in pre-silicon on the emulation platform.

·      Collaboration: Work closely with cross-functional teams including design, verification and SW development teams to understand issues in using the emulation platform.

·      Flow Automation: Develop and enhance automation scripts and flows using Python, Perl, and shell scripting to manage regressions, optimize runtime, and improve overall verification efficiency.

·      Vendor Collaboration: Interface with emulation platform vendors to debug and quickly resolve technical issues encountered with the tools.

·      The candidate must be able to work independently and proactively on allocated technical tasks.

Required Skills:

·      Proficiency in Hardware Description Languages (HDLs) such as Verilog and SystemVerilog.

·      SoC Knowledge: Solid understanding of SoC architectures and industry-standard protocols (e.g. AXI, PCIe, ETH, USB, HVM)

·      Experience with verification methodologies (UVM, SVA) and related verification environments, including C/C++ DPI is desirable.

·      Strong scripting skills in Python, Perl, Tcl, or Shell for automation.

·      Familiarity with debugging tools (e.g., Verdi, SimVision) and waveform analysis is desirable.

Education:

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.

Experience:

·      Proven experience of 5+ years in hardware verification and/or emulation roles.

·      Hands-on experience with at least one of the major commercial emulation platforms (Cadence Palladium, Synopsys ZeBu, or Siemens Veloce).

QFocus AI Pvt Ltd is an Equal Employment Opportunity employer.

Responsibilities

• End-to-End Embedded/DSP system design.

• Complex logic implementation using RTL coding techniques (preferably VHDL and HLS)

• Able to implement various complex algorithms and curve fitting/Neural network based algorithms inside the FPGA hardware.

• Writing modular RTL codes and design techniques using IPs.

• Simulating the design at various stages of development.

• CDC, STA, area/power optimizations, floor planning, linting.

• Interfacing high speed ADCs/DACs using state of the art data transfer links to FPGA.

• Using DDR RAM and SG-DMA for low latency, high-speed data transfer.

• Familiarity with high-speed communication systems viz. USB 3, PCIe, Gbe, 10 Gbe, 100

Gbe etc.

• Linux device driver development.

Skills

• VHDL/Verilog, C/C++, familiar with Xilinx development tools.

• Design knowledge of PCIe, LVDS, SPI, AXI, USB etc. interfaces.

• Ability to design using primitives instead of inferred design from RTL.

• Embedded linux device drivers, petalinux, exposure to yocto project.

• Exposure to various compression algorithms.

Desired Qualification/Experience

• Talent and zeal to work with new challenging system designs.

• Thorough understanding of digital systems.

• Hands-on experience on the RTL design, preferably with a repository of previous

projects

Responsibilities

 Develop an effective test suite based on the FPGA requirements.

 Testbench architecture with System Verilog and UVM

 Develop test environments based on the architecture.

 Develop Agents, Drivers, Monitors, Predictors, Scoreboard, and Sequences etc.

 Actively participate in a team environment, working with verification,

architecture, applications, and design teams to develop comprehensive

verification plans and address issues.

 Verification environment development/update for block level and system level.

 Own and drive verification related activities, provide technical support, and

proactively manage tasks to meet schedule goals.

 Define and develop effective functional assertions and coverpoints

 Debug the design issues and report through appropriate tools

 Code Coverage analysis and test case identification for improving the code

coverage.

 Perform timing simulations.

 Apply techniques and skills required to identify a root cause of a given issue and

very good debugging skills.

 Technical guidance to the junior engineers on verification tasks.

Qualifications

 Bachelor's/Master's degree in Engineering (Electronics and Communication or

VLSI )

 10+ years of Industry experience in development, integration & verification of

ASIC/FPGA.

 Protocols – PCIe, SPI, ARINC 429, Mil 1553, Image processing or similar.

 Hands on experience in developing System Verilog/UVM verification

environment from scratch.

 Hands on experience with Questa or similar advanced simulation tools.

 Hands on experience in DO-254 verification process.

 Experience in DOORS/Jama will be a plus.

 Experience in Video domain will be a plus.

Extensive hands on and teaching experience on Digital / SV /UVM/ Verilog / VHDL /DFT tools

Extensive experience in Back-end design

Experience on Mentor Graphics EDA flow is an added advantage

Responsible for development and support of Projects.

Responsible for Debugging the source codes in Verilog, SV, and UVM.

Responsible for Training Delivery and Support

Sound Knowledge on Digital / Verilog / VHDL / SV / UVM / DFT / Back-end design

3 to 8 years industry/teaching experience

Good communication skill