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Verilog Jobs in Pune

Explore top Verilog Job opportunities in Pune for Top Companies & Startups. All jobs are added by verified employees who can be contacted directly below.

FPGA Design Engineer
FPGA Design Engineer

Founded 1967
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Pune
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4 - 9 years
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Best in industry6 - 18 lacs/annum

Mandatory skills: FPGA, VHDL, Verilog (these are the skills the business is particularly looking for)   Complete product design flow knowledge including certification testing  Designed Hardware architecture of products  Worked on 8 16 32bit processors and done processor selections   Aware about architectures of processors   ARM, PowerPC  etc  Knowledge of external memory interfaces   serial, parallel and interfacing signals Good knowledge on types of interrupts Reset logic design   isolation techniques and unused pin terminations  Thorough on usage of debug interfaces like BDM  JTAG Good knowledge on Direct memory access and digital analog filters Termination circuits for impedance matching  Knowledge on DFM and DFT  Experience in designing high speed mixed hardware design projects  Usage of SI and PI analysis tool Experience in selecting required type of OPAMPs and design analog circuits   Interfacing analog circuits with digital circuits    Experience on interfacings external memories including DDR  DDR2 Preferred experience on atleast 1 or 2 audio video ports Experience on analog signal conditioning circuit design e g  filters  attenuators  etc    Experience of using complex high end functionality FPGA like Spartan 3E  Spartan 6 or Vertex 5  Cyclone 2 or 3 in atleast 1 or 2 projects  Should have done SI analysis of atleast one complex interface like SDRAM or DDR memory interfacing  Should be thorough on thermal issues and analysis  Should have done DFMEA for atleast one project  Should be thorough on high speed PCB layout  Should have complete knowledge on assembly process and aware about manufacturing of PCB  Should be able to decide on no  of layers requirement and layer stackup   Should be able to decide on test strategy and test setup for board bringup of given design Should be able to study issues in captured waveforms and timing captures Performed EMC and ENV testing Aware about EMC and ENV standards Experience in Functional Safety with respect to IEC 61508 and SIL 1  2 and 3 Levels Technical expertise     Tools  Schematic Design Tools like OrCAD  PADS  DxDesigner  Hyperlynx for SI and PI    Languages  C C    VHDL  Verilog

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Krupa Nadagouda
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Digital Verification Engineer
Digital Verification Engineer

Founded 2008
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Remote, Pune
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3 - 10 years
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Best in industry15 - 30 lacs/annum

Digital Verification Engineer About Company: Espressif Systems is a multinational, fabless semiconductor company established in 2008, with headquarters in Shanghai and offices in Greater China, India and Europe. We have a passionate team of engineers and scientists from all over the world, focused on developing cutting-edge WiFi-and-Bluetooth, low-power, IoT solutions. Among our popular products are the ESP8266 and ESP32 series of chips, modules and development boards. Job Description 1. Develop verification programs and define the verification environment according to design documentation, in order to conduct module- to chip-level verification; 2. Perform regression tests to improve verification coverage; 3. Assist the FPGA and software teams in FPGA prototype testing; 4. Collaborate with chip design engineers to find and fix any design defects; 5. Ensure the integrity of chip designs by supervising the design department when building verifiable design processes; 6. Carry out door-level simulation, with UPF verification methodology, to ensure successful chip tapeout. Job Prerequisites 1. Bachelor’s degree, or above, in Computer Engineering/Electronic Engineering/Communications Engineering, or other related disciplines; 2. 5+ years of work experience; 3. Familiarity with SoC and communication theory; 4. Familiarity with Verilog, proficiency in C/System Verilog verification; 5. Proficiency in Perl/Shell/Tcl scripts; 6. Experience in FPGA verification and/or chip tapeout is a plus; 7. Familiarity with VMM/UVM is a plus.

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Anuja Pawar
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