d

Responsibilities

• End-to-End Embedded/DSP system design.

• Complex logic implementation using RTL coding techniques (preferably VHDL and HLS)

• Able to implement various complex algorithms and curve fitting/Neural network based algorithms inside the FPGA hardware.

• Writing modular RTL codes and design techniques using IPs.

• Simulating the design at various stages of development.

• CDC, STA, area/power optimizations, floor planning, linting.

• Interfacing high speed ADCs/DACs using state of the art data transfer links to FPGA.

• Using DDR RAM and SG-DMA for low latency, high-speed data transfer.

• Familiarity with high-speed communication systems viz. USB 3, PCIe, Gbe, 10 Gbe, 100

Gbe etc.

• Linux device driver development.

Skills

• VHDL/Verilog, C/C++, familiar with Xilinx development tools.

• Design knowledge of PCIe, LVDS, SPI, AXI, USB etc. interfaces.

• Ability to design using primitives instead of inferred design from RTL.

• Embedded linux device drivers, petalinux, exposure to yocto project.

• Exposure to various compression algorithms.

Desired Qualification/Experience

• Talent and zeal to work with new challenging system designs.

• Thorough understanding of digital systems.

• Hands-on experience on the RTL design, preferably with a repository of previous

projects

1. Coding and Debugging in C language.
2. Knowledge on ARM based architectures of 8/16/32 Microcontrollers,UART, ADC, DAC,Ethernet, SPI,CAN,I2C and I2S.
3. FPGA RTL coding and Simulation using Verilog/VHDL

Qualification - BE/B.Tech (ECE), M.Sc.(Electronics)

Only Defense and Aerospace, Electronics, Semi-Conductors,

(No Automative industry)

AVANTEL LIMITED is a technology driven public limited company with focus on developing innovative wireless communication products and solutions to meet unique requirements of defense, railways, and telecom sectors. The organization is certified against AS 9100D and ISO 9001:2015 standards for Quality Management System. For more details visit www.avantel.in.

Are you a motivated and knowledgeable engineer ready to make a significant impact in the world of advanced technology? Designnex is on the lookout for a dynamic Design Verification Engineer to join our innovative team. In this exciting role, you will collaborate closely with customers to verify cutting-edge Interface IP (IIP) in their ASIC SoC/systems for groundbreaking next-generation products.

Key Responsibilities:

• Collaborate with customers to verify cutting-edge IPs in their ASIC SoC/systems.
• Provide support throughout the ASIC design cycle, focusing on design verification.
• Engage with the latest industry specifications and applications.
• Work with a diverse, worldwide team and interact with industry experts and leaders.

Key Qualifications:

• Experience: At least 2 years of related ASIC design verification experience. Strong academic backgrounds with relevant knowledge considered.

Skills:

• Experience in IP design verification flow of ASIC/SoC design (e.g., simulation, verification, RTL synthesis).
• Advanced lab experience (e.g., ATE, high-speed interface IP bring-up).
• Strong communication skills and ability to interact with peers from different geographies.
• Proficiency in UVM and SystemVerilog.
• Good to Know: PCIE and CXL specifications and design verification.

Preferred Experience:

• Technical knowledge of Interface IPs such as PCIe, Ethernet Protocols, Specification, Design, Verification, and Implementation.
• Proven track record in meeting tight schedules and handling multiple projects concurrently.
• Experience in various ASIC design cycles, including HIP/SIP integration into high-scale SoCs, design verification flows, physical implementation, SI/PI, and silicon bring-up in the lab.

Join Designnex and be part of a team at the forefront of technological advancements. Apply today and help shape the future of ASIC design and integration!

Job Description :

Own partition floorplanning for optimizing blocks for Power, Performance and Area.

Own execution from synthesis to place and route of partitions through all signoff including timing signoff, physical verification, EMIR signoff , Formal Equivalence, and Low Power Verification.

Have close collaboration with RTL team to help drive and resolve design issues related to block closure.

Understand tools, flows, and overall design methodology in design construction, signoff, and optimization with a data driven approach.

Implement robust clock distribution solutions using appropriate methods that meet design requirements.

Make good independent technical trade-offs between power, area, and timing (PPA)

Extensive hands on and teaching experience on Digital / SV /UVM/ Verilog / VHDL /DFT tools

Extensive experience in Back-end design

Experience on Mentor Graphics EDA flow is an added advantage

Responsible for development and support of Projects.

Responsible for Debugging the source codes in Verilog, SV, and UVM.

Responsible for Training Delivery and Support

Sound Knowledge on Digital / Verilog / VHDL / SV / UVM / DFT / Back-end design

3 to 8 years industry/teaching experience

Good communication skill

Job Title: Project Associate - Mixed Signal Design Profile
Industry: Wireless communication, 5G
Organization: 5G TestBed-IIT Hyderabad- Hyderabad

Job Description
Work Profile:
· Work on development of custom Analog circuit boards for applications related to RF, interfaces etc.
· Implement new features and bug fixes
· Verify analog/mixed-signal integrated circuits
· Develop test cases to verify new features and bug fixes
· Review and update the user manuals for software tools.
· Supporting digital modelling of analog circuits for mixed-signal verification
· Creating design specifications and circuit schematics
· Work both independently and in a team environment, with the opportunity to provide technical leadership to other members of the engineering team
· Create and/or modify specification documents detailing system design and enhancements to meet marketing requirements
· Collaborate with others in the creation of technical reports, whitepapers, and user documentation

Requisites:
· EE/EEE/ECE graduate, undergraduate degree from reputed Tier 1 or Tier 2 colleges .
· Strong knowledge of analog integrated circuit design fundamentals
· Proven experience taking designs from concept to production
· Experience in analog/mixed-signal IC design & verification
· Understanding of BJT, CMOS and Op-Amp technologies.
· Good understanding of analog/mixed-signal design flows (Cadence, Synopsys)
· Transistor and system level simulation skills
· Discrete time and continuous time signal processing skills
· Strong lab and silicon validation skills
· Verilog based digital design and test bench development, is a plus
· Strong communication skills, both written and verbal
About us:
For more details please visit: http://5g.iith.ac.in/
IIT Hyderabad in collaboration with top Indian institutes including IITM, CEWiT, IITD, IITK, IISC and SAMEER is building the largest 5G testbed of the country, with the support of Department of Telecommunications (DoT) Govt. of India. This project will create a 5G prototype and testing platform that will be developed under the guidance of IIT-H faculty.
The project will deliver an end-to-end 5G testbed comprising 5G BS and UE nodes that support enhanced mobile broadband (eMBB), Ultra low latency communication (URLLC), and massive MTC including NB IoT services. The operating frequently includes both sub 6 GHz and mmwave frequencies. The system will exceed IMT 2020 5G performance requirements including Low Mobility Large Cell (i.e.., LMLC) targets introduced by India at ITU.
The 'Indigenous 5G Testbed' project is a long-term effort with a team of 100+ researchers/engineers based out of IIT-H campus.