
About Alten calsoft labs
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8+ years
Domain skills
• Expert in FPGA flows with Xilinx, including compilation, synthesis, debug, performance and implementation of advanced features
• Good Hands on Linting, Static Timing Analysis, Equivalence Checking & Clock Domain Crossing.
• Experience in developing verification environment to verify developed items using self-checking test benches, BFMs, checkers/Monitors & Score boards using VHDL/verilog.
• Prior experience in integrating Nios, MPIS, MicroBlaze, ARM Cortex, etc. GTX / GTH transceivers & 10GE MAC / DMA controller / PCIe Gen3 / CPRI / JESD / FFT IP core
• Common control interfaces design, like AMBA AXI, UART, SPI, I2C, DDR, Ethernet, USB, etc..
• Knowledge on programming languages such as Verilog, VHDL and system Verilog
• Experience with any scripting language for automation (Perl/TCL/Python).
• Familiar with standard FPGA HW bring-up activities and testing
• Experience with HW measuring tools like oscilloscopes, Signal analysers, JTAG Emulators
Responsibilities
• End-to-End Embedded/DSP system design.
• Complex logic implementation using RTL coding techniques (preferably VHDL and HLS)
• Able to implement various complex algorithms and curve fitting/Neural network based algorithms inside the FPGA hardware.
• Writing modular RTL codes and design techniques using IPs.
• Simulating the design at various stages of development.
• CDC, STA, area/power optimizations, floor planning, linting.
• Interfacing high speed ADCs/DACs using state of the art data transfer links to FPGA.
• Using DDR RAM and SG-DMA for low latency, high-speed data transfer.
• Familiarity with high-speed communication systems viz. USB 3, PCIe, Gbe, 10 Gbe, 100
Gbe etc.
• Linux device driver development.
Skills
• VHDL/Verilog, C/C++, familiar with Xilinx development tools.
• Design knowledge of PCIe, LVDS, SPI, AXI, USB etc. interfaces.
• Ability to design using primitives instead of inferred design from RTL.
• Embedded linux device drivers, petalinux, exposure to yocto project.
• Exposure to various compression algorithms.
Desired Qualification/Experience
• Talent and zeal to work with new challenging system designs.
• Thorough understanding of digital systems.
• Hands-on experience on the RTL design, preferably with a repository of previous
projects
- Coding and Debugging in C language.
- Knowledge on ARM based architectures of 8/16/32 Microcontrollers,UART, ADC, DAC,Ethernet, SPI,CAN,I2C and I2S.
- FPGA RTL coding and Simulation using Verilog/VHDL
Qualification - BE/B.Tech (ECE), M.Sc.(Electronics)
Only Defense and Aerospace, Electronics, Semi-Conductors,
(No Automative industry)
AVANTEL LIMITED is a technology driven public limited company with focus on developing innovative wireless communication products and solutions to meet unique requirements of defense, railways, and telecom sectors. The organization is certified against AS 9100D and ISO 9001:2015 standards for Quality Management System. For more details visit www.avantel.in.
Job Description :
Own partition floorplanning for optimizing blocks for Power, Performance and Area.
Own execution from synthesis to place and route of partitions through all signoff including timing signoff, physical verification, EMIR signoff , Formal Equivalence, and Low Power Verification.
Have close collaboration with RTL team to help drive and resolve design issues related to block closure.
Understand tools, flows, and overall design methodology in design construction, signoff, and optimization with a data driven approach.
Implement robust clock distribution solutions using appropriate methods that meet design requirements.
Make good independent technical trade-offs between power, area, and timing (PPA)
Responsibilities
Develop an effective test suite based on the FPGA requirements.
Testbench architecture with System Verilog and UVM
Develop test environments based on the architecture.
Develop Agents, Drivers, Monitors, Predictors, Scoreboard, and Sequences etc.
Actively participate in a team environment, working with verification,
architecture, applications, and design teams to develop comprehensive
verification plans and address issues.
Verification environment development/update for block level and system level.
Own and drive verification related activities, provide technical support, and
proactively manage tasks to meet schedule goals.
Define and develop effective functional assertions and coverpoints
Debug the design issues and report through appropriate tools
Code Coverage analysis and test case identification for improving the code
coverage.
Perform timing simulations.
Apply techniques and skills required to identify a root cause of a given issue and
very good debugging skills.
Technical guidance to the junior engineers on verification tasks.
Qualifications
Bachelor's/Master's degree in Engineering (Electronics and Communication or
VLSI )
10+ years of Industry experience in development, integration & verification of
ASIC/FPGA.
Protocols – PCIe, SPI, ARINC 429, Mil 1553, Image processing or similar.
Hands on experience in developing System Verilog/UVM verification
environment from scratch.
Hands on experience with Questa or similar advanced simulation tools.
Hands on experience in DO-254 verification process.
Experience in DOORS/Jama will be a plus.
Experience in Video domain will be a plus.
Job Description
Extensive hands on and teaching experience on Digital / SV /UVM/ Verilog / VHDL /DFT tools
Extensive experience in Back-end design
Experience on Mentor Graphics EDA flow is an added advantage
Responsible for development and support of Projects.
Responsible for Debugging the source codes in Verilog, SV, and UVM.
Responsible for Training Delivery and Support
Desired Candidate Profile
Sound Knowledge on Digital / Verilog / VHDL / SV / UVM / DFT / Back-end design
3 to 8 years industry/teaching experience
Good communication skill

Skills/Experience
Experience with complete flows involving timing closure of high speed digital design using scripting languages and design automation.
Has deep knowledge of Xilinx FPGA implementation and tools.
Experience in state of the art tools and flows.
Working knowledge in Verilog and System Verilog.
Job Requirements
Bachelors in Electronics Engineering.
Strong knowledge of ASIC and/or FPGA design methodology and should be well versed in front-end design, simulation, and verification CAD tools.
Relevant FPGA/ASIC engineering design and verification experience is entertained.
Excellent verbal, written and communication skills are required.
Excellent follow-through, motivation, and persistence
Strong technical judgment and decision making abilities.
Knowledge of digital board design and signal integrity principles is a plus.

