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Job Responsibilities:

• Assist in the design, development, and maintenance of high-quality Android applications using Java/Kotlin.
• Work with Android Studio to write clean, efficient, and well-documented code.
• Implement and adhere to MVVM (Model-View-ViewModel) architectural patterns to ensure scalable and maintainable applications.
• Utilize Data Binding to streamline UI development and improve code readability.
• Develop user interfaces with a strong understanding of various Layouts (ConstraintLayout, LinearLayout, RelativeLayout, etc.) and responsive design principles.
• Integrate applications with RESTful Webservices using libraries like Retrofit to connect with backend services and handle data efficiently.
• Gain experience in interacting with databases, including basic operations with SQLite Database (Creating, Updating/Querying) for local data storage and understanding of server-side data interaction.
• Apply Debugging Skills using tools such as Logcat, Android Debugger (Debug), and Lint for identifying and resolving issues, and optimizing application performance.
• Leverage Plugin Tools like ADB Idea, Codata, and Lombok Plugin (if applicable) to enhance development workflow and productivity.
• Work with various Android APIs to implement new features and functionality.
• Participate in Testing the Android Application, including unit testing and collaborating with QA for functional and integration testing.
• Perform Lint for Code Inspection to ensure code quality, consistency, and adherence to best practices.
• Learn and apply fundamental Design Patterns (e.g., Singleton, Observer) in Android development.
• Collaborate effectively with cross-functional teams, including product managers, UI/UX designers, and backend developers, to define, design, and ship new features.
• Continuously discover, evaluate, and implement new technologies to maximize development efficiency and improve application performance.
• Stay up-to-date with the latest Android development trends and best practices.

Required Skills and Qualifications:

• Bachelor's degree in Computer Science, Information Technology, or a related field (or equivalent practical experience).
• 0-2 years of hands-on experience in Android application development.
• Solid understanding of Android SDK and Android Studio.
• Proficiency in at least one of the primary Android programming languages: Java or Kotlin.
• Familiarity with MVVM architecture.
• Basic knowledge of Data Binding.
• Understanding of various Android Layouts.
• Exposure to SQLite Database and concepts of server-side interaction.
• Familiarity with Retrofit for API consumption.
• Demonstrated Debugging Skills using relevant Android tools.
• Awareness of common Plugin Tools for Android development.
• Basic understanding of Android APIs.
• Knowledge of RESTful Webservices principles.
• Experience with testing methodologies for Android applications.
• Ability to use Lint for Code Inspection.
• Eagerness to learn and apply Design Patterns.
• Strong problem-solving abilities and attention to detail.
• Excellent communication and teamwork skills.
• A portfolio of personal or academic Android projects is a strong plus.

We are seeking a highly skilled and passionate Hardware Emulation Engineer to join our team working withthe best in the Industry, developing innovative ASIC solutions for data center and AI Infrastructure. As an Hardware Emulation Engineer, you will be at the forefront of pre-silicon validation, ensuring the highest quality and functionality of our hardware before it goes into production.

Key Responsibilities:

·      Emulation Environment Development: Build and maintain pre-silicon emulation platforms using industry-standard systems such as Cadence Palladium or Synopsys ZeBu or Veloce Strato, Primo

·      Model Integration and Optimization: Integrate the RTL design onto the emulation platform by ensuring synthesizability, optimize build efficiency and performance, and work with high-performance transactors and emulation testbenches (e.g., using SystemVerilog, C/C++, Python).

·      Flush out emulation flow issues by performing smoke verification

·      Support validation team in execute comprehensive test content, including bare-metal and OS-based tests, to accelerate bug finding in pre-silicon on the emulation platform.

·      Collaboration: Work closely with cross-functional teams including design, verification and SW development teams to understand issues in using the emulation platform.

·      Flow Automation: Develop and enhance automation scripts and flows using Python, Perl, and shell scripting to manage regressions, optimize runtime, and improve overall verification efficiency.

·      Vendor Collaboration: Interface with emulation platform vendors to debug and quickly resolve technical issues encountered with the tools.

·      The candidate must be able to work independently and proactively on allocated technical tasks.

Required Skills:

·      Proficiency in Hardware Description Languages (HDLs) such as Verilog and SystemVerilog.

·      SoC Knowledge: Solid understanding of SoC architectures and industry-standard protocols (e.g. AXI, PCIe, ETH, USB, HVM)

·      Experience with verification methodologies (UVM, SVA) and related verification environments, including C/C++ DPI is desirable.

·      Strong scripting skills in Python, Perl, Tcl, or Shell for automation.

·      Familiarity with debugging tools (e.g., Verdi, SimVision) and waveform analysis is desirable.

Education:

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.

Experience:

·      Proven experience of 5+ years in hardware verification and/or emulation roles.

·      Hands-on experience with at least one of the major commercial emulation platforms (Cadence Palladium, Synopsys ZeBu, or Siemens Veloce).

QFocus AI Pvt Ltd is an Equal Employment Opportunity employer.

1. Coding and Debugging in C language.
2. Knowledge on ARM based architectures of 8/16/32 Microcontrollers,UART, ADC, DAC,Ethernet, SPI,CAN,I2C and I2S.
3. FPGA RTL coding and Simulation using Verilog/VHDL

Qualification - BE/B.Tech (ECE), M.Sc.(Electronics)

Only Defense and Aerospace, Electronics, Semi-Conductors,

(No Automative industry)

AVANTEL LIMITED is a technology driven public limited company with focus on developing innovative wireless communication products and solutions to meet unique requirements of defense, railways, and telecom sectors. The organization is certified against AS 9100D and ISO 9001:2015 standards for Quality Management System. For more details visit www.avantel.in.

Responsibilities

 Develop an effective test suite based on the FPGA requirements.

 Testbench architecture with System Verilog and UVM

 Develop test environments based on the architecture.

 Develop Agents, Drivers, Monitors, Predictors, Scoreboard, and Sequences etc.

 Actively participate in a team environment, working with verification,

architecture, applications, and design teams to develop comprehensive

verification plans and address issues.

 Verification environment development/update for block level and system level.

 Own and drive verification related activities, provide technical support, and

proactively manage tasks to meet schedule goals.

 Define and develop effective functional assertions and coverpoints

 Debug the design issues and report through appropriate tools

 Code Coverage analysis and test case identification for improving the code

coverage.

 Perform timing simulations.

 Apply techniques and skills required to identify a root cause of a given issue and

very good debugging skills.

 Technical guidance to the junior engineers on verification tasks.

Qualifications

 Bachelor's/Master's degree in Engineering (Electronics and Communication or

VLSI )

 10+ years of Industry experience in development, integration & verification of

ASIC/FPGA.

 Protocols – PCIe, SPI, ARINC 429, Mil 1553, Image processing or similar.

 Hands on experience in developing System Verilog/UVM verification

environment from scratch.

 Hands on experience with Questa or similar advanced simulation tools.

 Hands on experience in DO-254 verification process.

 Experience in DOORS/Jama will be a plus.

 Experience in Video domain will be a plus.

Extensive hands on and teaching experience on Digital / SV /UVM/ Verilog / VHDL /DFT tools

Extensive experience in Back-end design

Experience on Mentor Graphics EDA flow is an added advantage

Responsible for development and support of Projects.

Responsible for Debugging the source codes in Verilog, SV, and UVM.

Responsible for Training Delivery and Support

Sound Knowledge on Digital / Verilog / VHDL / SV / UVM / DFT / Back-end design

3 to 8 years industry/teaching experience

Good communication skill

About Company

Espressif Systems is a multinational, fabless semiconductor company established in 2008, with headquarters in Shanghai and offices in Greater China, India and Europe. We have a passionate team of engineers and scientists from all over the world, focused on developing cutting-edge WiFi-and-Bluetooth, low-power, IoT solutions. Among our popular products are the ESP8266 and ESP32 series of chips, modules and development boards. Espressif has opened a Technology Center in Pune(Baner), India, which will focus on embedded software engineering and IoT solutions development for our growing customers.

At Espressif, communication, collaboration and innovation are of paramount importance. That's why professionals and engineers from around the world have chosen to further their careers at Espressif Systems. They are passionate and committed to developing innovative products. And they are here to ensure that fast,secure and green IoT technology can be available to all. Come and join Espressif, so that you, too, can partake in Espressif's mission in the IoT industry.

BASIC QUALIFICATIONS

• M.Tech/B. Tech in the field of VLSI/Electronics engineering. 
• Proficiency in UVM/SV and C/C++ based functional verification 
• Experience in UPF based low power design verification
• Automation skills in PERL and/or TCL and/or Shell* 
• Team player, with good problem solving and communication skills. 

JOB DESCRIPTION 

• Drive functional verification at IP/SoC level using UVM/SV test bench
• Work closely with design team to define comprehensive feature test plans
• Perform functional and code coverage for logic verification sign-off
• Must have worked on ARM/RISC-V CPU based designs
• Must have performed gate level sim at SoC level
• Pre and Post-silicon debug/validation experience will be a plus

INTERPERSONAL SKILLS:

• Energetic, self-motivated
• Pro-active, oriented on execution
• Attentive to details and quality
• Team player
• Good communications and reporting skills