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Job Title : Hardware Design Developer – Verilog

Employment Type : Full-Time Contract (8 hours/day)

Location : Remote

Experience : 3+ Years (Mandatory)

Notice Period : Immediate

Job Overview :

We are looking for an experienced Hardware Design Developer to leverage hardware design platforms for generating training data to enhance enterprise LLMs' capabilities. This role offers a unique opportunity to directly impact AI advancements by optimizing hardware designs for training and benchmarking large language models.

Key Responsibilities :

• Develop, configure, and customize hardware design platforms to generate training data for enterprise LLMs.
• Work closely with research teams to translate requirements into actionable insights.
• Ensure high-quality coding, debugging, and documentation to optimize hardware design solutions.
• Collaborate with cross-functional teams to improve LLM performance and automation capabilities.

Required Skills & Experience:

• BS/MS in Electrical Engineering or related field.
• 3 to 5 Years of hardware design development experience.
• Expertise in HDLs (Verilog, SystemVerilog, VHDL, SystemC).
• Strong background in scripting, front-end workflows, and verification processes.
• Familiarity with Synopsys, Cadence, or open-source toolchains.
• Excellent problem-solving and collaboration skills.

Preferred Qualifications :

• Expertise in UVM environments, Formal Verification, and Lint refinement.
• Experience with Computer Architecture, Assembly Debugging, and Assertion Coding (SVA).
• Familiarity with Machine Learning and AI systems.

Mandatory Technical Skills :

• Min 2 Years of relevant experience in Hardware Design and/or Verification.
• Experience with at least one of the following:
• ASIC, VLSI, FPGA, SoC development.
• SystemVerilog, Verilog, Testbench development, and Verification.
• Strong understanding of IP Development and Verification.

Note: This role focuses on LLM training using hardware design, not traditional project development.

Responsibilities

• End-to-End Embedded/DSP system design.

• Complex logic implementation using RTL coding techniques (preferably VHDL and HLS)

• Able to implement various complex algorithms and curve fitting/Neural network based algorithms inside the FPGA hardware.

• Writing modular RTL codes and design techniques using IPs.

• Simulating the design at various stages of development.

• CDC, STA, area/power optimizations, floor planning, linting.

• Interfacing high speed ADCs/DACs using state of the art data transfer links to FPGA.

• Using DDR RAM and SG-DMA for low latency, high-speed data transfer.

• Familiarity with high-speed communication systems viz. USB 3, PCIe, Gbe, 10 Gbe, 100

Gbe etc.

• Linux device driver development.

Skills

• VHDL/Verilog, C/C++, familiar with Xilinx development tools.

• Design knowledge of PCIe, LVDS, SPI, AXI, USB etc. interfaces.

• Ability to design using primitives instead of inferred design from RTL.

• Embedded linux device drivers, petalinux, exposure to yocto project.

• Exposure to various compression algorithms.

Desired Qualification/Experience

• Talent and zeal to work with new challenging system designs.

• Thorough understanding of digital systems.

• Hands-on experience on the RTL design, preferably with a repository of previous

projects

1. Coding and Debugging in C language.
2. Knowledge on ARM based architectures of 8/16/32 Microcontrollers,UART, ADC, DAC,Ethernet, SPI,CAN,I2C and I2S.
3. FPGA RTL coding and Simulation using Verilog/VHDL

Qualification - BE/B.Tech (ECE), M.Sc.(Electronics)

Only Defense and Aerospace, Electronics, Semi-Conductors,

(No Automative industry)

AVANTEL LIMITED is a technology driven public limited company with focus on developing innovative wireless communication products and solutions to meet unique requirements of defense, railways, and telecom sectors. The organization is certified against AS 9100D and ISO 9001:2015 standards for Quality Management System. For more details visit www.avantel.in.

Job Description :

Own partition floorplanning for optimizing blocks for Power, Performance and Area.

Own execution from synthesis to place and route of partitions through all signoff including timing signoff, physical verification, EMIR signoff , Formal Equivalence, and Low Power Verification.

Have close collaboration with RTL team to help drive and resolve design issues related to block closure.

Understand tools, flows, and overall design methodology in design construction, signoff, and optimization with a data driven approach.

Implement robust clock distribution solutions using appropriate methods that meet design requirements.

Make good independent technical trade-offs between power, area, and timing (PPA)

StartUp engaged in inventing and innovating Smart Energy Meters and related Technologies (OEM) requires Embedded Engineers. Following re-innovation principle and Technology First direction, we design Technologies to deliver our Vision of the highest Quality Products and Technologies. The candidate's responsibilities include IoT (COSEM/DLMS), technology integration. Required skills include Embedded C and C++ and knowledge of Electrical and Electronics.

Job Title: Project Associate - Mixed Signal Design Profile
Industry: Wireless communication, 5G
Organization: 5G TestBed-IIT Hyderabad- Hyderabad

Job Description
Work Profile:
· Work on development of custom Analog circuit boards for applications related to RF, interfaces etc.
· Implement new features and bug fixes
· Verify analog/mixed-signal integrated circuits
· Develop test cases to verify new features and bug fixes
· Review and update the user manuals for software tools.
· Supporting digital modelling of analog circuits for mixed-signal verification
· Creating design specifications and circuit schematics
· Work both independently and in a team environment, with the opportunity to provide technical leadership to other members of the engineering team
· Create and/or modify specification documents detailing system design and enhancements to meet marketing requirements
· Collaborate with others in the creation of technical reports, whitepapers, and user documentation

Requisites:
· EE/EEE/ECE graduate, undergraduate degree from reputed Tier 1 or Tier 2 colleges .
· Strong knowledge of analog integrated circuit design fundamentals
· Proven experience taking designs from concept to production
· Experience in analog/mixed-signal IC design & verification
· Understanding of BJT, CMOS and Op-Amp technologies.
· Good understanding of analog/mixed-signal design flows (Cadence, Synopsys)
· Transistor and system level simulation skills
· Discrete time and continuous time signal processing skills
· Strong lab and silicon validation skills
· Verilog based digital design and test bench development, is a plus
· Strong communication skills, both written and verbal
About us:
For more details please visit: http://5g.iith.ac.in/
IIT Hyderabad in collaboration with top Indian institutes including IITM, CEWiT, IITD, IITK, IISC and SAMEER is building the largest 5G testbed of the country, with the support of Department of Telecommunications (DoT) Govt. of India. This project will create a 5G prototype and testing platform that will be developed under the guidance of IIT-H faculty.
The project will deliver an end-to-end 5G testbed comprising 5G BS and UE nodes that support enhanced mobile broadband (eMBB), Ultra low latency communication (URLLC), and massive MTC including NB IoT services. The operating frequently includes both sub 6 GHz and mmwave frequencies. The system will exceed IMT 2020 5G performance requirements including Low Mobility Large Cell (i.e.., LMLC) targets introduced by India at ITU.
The 'Indigenous 5G Testbed' project is a long-term effort with a team of 100+ researchers/engineers based out of IIT-H campus.