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Job Title : Hardware Design Developer – Verilog

Employment Type : Full-Time Contract (8 hours/day)

Location : Remote

Experience : 3+ Years (Mandatory)

Notice Period : Immediate

Job Overview :

We are looking for an experienced Hardware Design Developer to leverage hardware design platforms for generating training data to enhance enterprise LLMs' capabilities. This role offers a unique opportunity to directly impact AI advancements by optimizing hardware designs for training and benchmarking large language models.

Key Responsibilities :

• Develop, configure, and customize hardware design platforms to generate training data for enterprise LLMs.
• Work closely with research teams to translate requirements into actionable insights.
• Ensure high-quality coding, debugging, and documentation to optimize hardware design solutions.
• Collaborate with cross-functional teams to improve LLM performance and automation capabilities.

Required Skills & Experience:

• BS/MS in Electrical Engineering or related field.
• 3 to 5 Years of hardware design development experience.
• Expertise in HDLs (Verilog, SystemVerilog, VHDL, SystemC).
• Strong background in scripting, front-end workflows, and verification processes.
• Familiarity with Synopsys, Cadence, or open-source toolchains.
• Excellent problem-solving and collaboration skills.

Preferred Qualifications :

• Expertise in UVM environments, Formal Verification, and Lint refinement.
• Experience with Computer Architecture, Assembly Debugging, and Assertion Coding (SVA).
• Familiarity with Machine Learning and AI systems.

Mandatory Technical Skills :

• Min 2 Years of relevant experience in Hardware Design and/or Verification.
• Experience with at least one of the following:
• ASIC, VLSI, FPGA, SoC development.
• SystemVerilog, Verilog, Testbench development, and Verification.
• Strong understanding of IP Development and Verification.

Note: This role focuses on LLM training using hardware design, not traditional project development.

Job Responsibilities:

• Assist in the design, development, and maintenance of high-quality Android applications using Java/Kotlin.
• Work with Android Studio to write clean, efficient, and well-documented code.
• Implement and adhere to MVVM (Model-View-ViewModel) architectural patterns to ensure scalable and maintainable applications.
• Utilize Data Binding to streamline UI development and improve code readability.
• Develop user interfaces with a strong understanding of various Layouts (ConstraintLayout, LinearLayout, RelativeLayout, etc.) and responsive design principles.
• Integrate applications with RESTful Webservices using libraries like Retrofit to connect with backend services and handle data efficiently.
• Gain experience in interacting with databases, including basic operations with SQLite Database (Creating, Updating/Querying) for local data storage and understanding of server-side data interaction.
• Apply Debugging Skills using tools such as Logcat, Android Debugger (Debug), and Lint for identifying and resolving issues, and optimizing application performance.
• Leverage Plugin Tools like ADB Idea, Codata, and Lombok Plugin (if applicable) to enhance development workflow and productivity.
• Work with various Android APIs to implement new features and functionality.
• Participate in Testing the Android Application, including unit testing and collaborating with QA for functional and integration testing.
• Perform Lint for Code Inspection to ensure code quality, consistency, and adherence to best practices.
• Learn and apply fundamental Design Patterns (e.g., Singleton, Observer) in Android development.
• Collaborate effectively with cross-functional teams, including product managers, UI/UX designers, and backend developers, to define, design, and ship new features.
• Continuously discover, evaluate, and implement new technologies to maximize development efficiency and improve application performance.
• Stay up-to-date with the latest Android development trends and best practices.

Required Skills and Qualifications:

• Bachelor's degree in Computer Science, Information Technology, or a related field (or equivalent practical experience).
• 0-2 years of hands-on experience in Android application development.
• Solid understanding of Android SDK and Android Studio.
• Proficiency in at least one of the primary Android programming languages: Java or Kotlin.
• Familiarity with MVVM architecture.
• Basic knowledge of Data Binding.
• Understanding of various Android Layouts.
• Exposure to SQLite Database and concepts of server-side interaction.
• Familiarity with Retrofit for API consumption.
• Demonstrated Debugging Skills using relevant Android tools.
• Awareness of common Plugin Tools for Android development.
• Basic understanding of Android APIs.
• Knowledge of RESTful Webservices principles.
• Experience with testing methodologies for Android applications.
• Ability to use Lint for Code Inspection.
• Eagerness to learn and apply Design Patterns.
• Strong problem-solving abilities and attention to detail.
• Excellent communication and teamwork skills.
• A portfolio of personal or academic Android projects is a strong plus.

Job Description :

Own partition floorplanning for optimizing blocks for Power, Performance and Area.

Own execution from synthesis to place and route of partitions through all signoff including timing signoff, physical verification, EMIR signoff , Formal Equivalence, and Low Power Verification.

Have close collaboration with RTL team to help drive and resolve design issues related to block closure.

Understand tools, flows, and overall design methodology in design construction, signoff, and optimization with a data driven approach.

Implement robust clock distribution solutions using appropriate methods that meet design requirements.

Make good independent technical trade-offs between power, area, and timing (PPA)

Responsibilities

 Develop an effective test suite based on the FPGA requirements.

 Testbench architecture with System Verilog and UVM

 Develop test environments based on the architecture.

 Develop Agents, Drivers, Monitors, Predictors, Scoreboard, and Sequences etc.

 Actively participate in a team environment, working with verification,

architecture, applications, and design teams to develop comprehensive

verification plans and address issues.

 Verification environment development/update for block level and system level.

 Own and drive verification related activities, provide technical support, and

proactively manage tasks to meet schedule goals.

 Define and develop effective functional assertions and coverpoints

 Debug the design issues and report through appropriate tools

 Code Coverage analysis and test case identification for improving the code

coverage.

 Perform timing simulations.

 Apply techniques and skills required to identify a root cause of a given issue and

very good debugging skills.

 Technical guidance to the junior engineers on verification tasks.

Qualifications

 Bachelor's/Master's degree in Engineering (Electronics and Communication or

VLSI )

 10+ years of Industry experience in development, integration & verification of

ASIC/FPGA.

 Protocols – PCIe, SPI, ARINC 429, Mil 1553, Image processing or similar.

 Hands on experience in developing System Verilog/UVM verification

environment from scratch.

 Hands on experience with Questa or similar advanced simulation tools.

 Hands on experience in DO-254 verification process.

 Experience in DOORS/Jama will be a plus.

 Experience in Video domain will be a plus.

Extensive hands on and teaching experience on Digital / SV /UVM/ Verilog / VHDL /DFT tools

Extensive experience in Back-end design

Experience on Mentor Graphics EDA flow is an added advantage

Responsible for development and support of Projects.

Responsible for Debugging the source codes in Verilog, SV, and UVM.

Responsible for Training Delivery and Support

Sound Knowledge on Digital / Verilog / VHDL / SV / UVM / DFT / Back-end design

3 to 8 years industry/teaching experience

Good communication skill

StartUp engaged in inventing and innovating Smart Energy Meters and related Technologies (OEM) requires Embedded Engineers. Following re-innovation principle and Technology First direction, we design Technologies to deliver our Vision of the highest Quality Products and Technologies. The candidate's responsibilities include IoT (COSEM/DLMS), technology integration. Required skills include Embedded C and C++ and knowledge of Electrical and Electronics.

Skills/Experience

Experience with complete flows involving timing closure of high speed digital design using scripting languages and design automation.

Has deep knowledge of Xilinx FPGA implementation and tools.

Experience in state of the art tools and flows.

Working knowledge in Verilog and System Verilog.

 Job Requirements

Bachelors in Electronics Engineering.

Strong knowledge of ASIC and/or FPGA design methodology and should be well versed in front-end design, simulation, and verification CAD tools.

Relevant FPGA/ASIC engineering design and verification experience is entertained.

Excellent verbal, written and communication skills are required.

Excellent follow-through, motivation, and persistence

Strong technical judgment and decision making abilities.

Knowledge of digital board design and signal integrity principles is a plus.

About Company

Espressif Systems is a multinational, fabless semiconductor company established in 2008, with headquarters in Shanghai and offices in Greater China, India and Europe. We have a passionate team of engineers and scientists from all over the world, focused on developing cutting-edge WiFi-and-Bluetooth, low-power, IoT solutions. Among our popular products are the ESP8266 and ESP32 series of chips, modules and development boards. Espressif has opened a Technology Center in Pune(Baner), India, which will focus on embedded software engineering and IoT solutions development for our growing customers.

At Espressif, communication, collaboration and innovation are of paramount importance. That's why professionals and engineers from around the world have chosen to further their careers at Espressif Systems. They are passionate and committed to developing innovative products. And they are here to ensure that fast,secure and green IoT technology can be available to all. Come and join Espressif, so that you, too, can partake in Espressif's mission in the IoT industry.

BASIC QUALIFICATIONS

• M.Tech/B. Tech in the field of VLSI/Electronics engineering. 
• Proficiency in UVM/SV and C/C++ based functional verification 
• Experience in UPF based low power design verification
• Automation skills in PERL and/or TCL and/or Shell* 
• Team player, with good problem solving and communication skills. 

JOB DESCRIPTION 

• Drive functional verification at IP/SoC level using UVM/SV test bench
• Work closely with design team to define comprehensive feature test plans
• Perform functional and code coverage for logic verification sign-off
• Must have worked on ARM/RISC-V CPU based designs
• Must have performed gate level sim at SoC level
• Pre and Post-silicon debug/validation experience will be a plus

INTERPERSONAL SKILLS:

• Energetic, self-motivated
• Pro-active, oriented on execution
• Attentive to details and quality
• Team player
• Good communications and reporting skills