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Job Description :
Own partition floorplanning for optimizing blocks for Power, Performance and Area.
Own execution from synthesis to place and route of partitions through all signoff including timing signoff, physical verification, EMIR signoff , Formal Equivalence, and Low Power Verification.
Have close collaboration with RTL team to help drive and resolve design issues related to block closure.
Understand tools, flows, and overall design methodology in design construction, signoff, and optimization with a data driven approach.
Implement robust clock distribution solutions using appropriate methods that meet design requirements.
Make good independent technical trade-offs between power, area, and timing (PPA)
Job Description
Extensive hands on and teaching experience on Digital / SV /UVM/ Verilog / VHDL /DFT tools
Extensive experience in Back-end design
Experience on Mentor Graphics EDA flow is an added advantage
Responsible for development and support of Projects.
Responsible for Debugging the source codes in Verilog, SV, and UVM.
Responsible for Training Delivery and Support
Desired Candidate Profile
Sound Knowledge on Digital / Verilog / VHDL / SV / UVM / DFT / Back-end design
3 to 8 years industry/teaching experience
Good communication skill

StartUp engaged in inventing and innovating Smart Energy Meters and related Technologies (OEM) requires Embedded Engineers. Following re-innovation principle and Technology First direction, we design Technologies to deliver our Vision of the highest Quality Products and Technologies. The candidate's responsibilities include IoT (COSEM/DLMS), technology integration. Required skills include Embedded C and C++ and knowledge of Electrical and Electronics.
1.SV, UVM, USB, DDR, PCIE, Ethernet, Axi, MIPI. Any one of the protocols will
be added advantage.
2.Experience in verification of complex IPs or SoCs.
3. Expertise in SoC Verification using C and SV/UVM.Expertise in AMBA
protocols
4. AXI/AHB/APB and experience in working with ARM Processors.
5. Expertise in Test Plan creation and Verification technologies like Code
Coverage, Functional Coverage and Assertions.
Job Title: Project Associate - Mixed Signal Design Profile
Industry: Wireless communication, 5G
Organization: 5G TestBed-IIT Hyderabad- Hyderabad
Job Description
Work Profile:
· Work on development of custom Analog circuit boards for applications related to RF, interfaces etc.
· Implement new features and bug fixes
· Verify analog/mixed-signal integrated circuits
· Develop test cases to verify new features and bug fixes
· Review and update the user manuals for software tools.
· Supporting digital modelling of analog circuits for mixed-signal verification
· Creating design specifications and circuit schematics
· Work both independently and in a team environment, with the opportunity to provide technical leadership to other members of the engineering team
· Create and/or modify specification documents detailing system design and enhancements to meet marketing requirements
· Collaborate with others in the creation of technical reports, whitepapers, and user documentation
Requisites:
· EE/EEE/ECE graduate, undergraduate degree from reputed Tier 1 or Tier 2 colleges .
· Strong knowledge of analog integrated circuit design fundamentals
· Proven experience taking designs from concept to production
· Experience in analog/mixed-signal IC design & verification
· Understanding of BJT, CMOS and Op-Amp technologies.
· Good understanding of analog/mixed-signal design flows (Cadence, Synopsys)
· Transistor and system level simulation skills
· Discrete time and continuous time signal processing skills
· Strong lab and silicon validation skills
· Verilog based digital design and test bench development, is a plus
· Strong communication skills, both written and verbal
About us:
For more details please visit: http://5g.iith.ac.in/
IIT Hyderabad in collaboration with top Indian institutes including IITM, CEWiT, IITD, IITK, IISC and SAMEER is building the largest 5G testbed of the country, with the support of Department of Telecommunications (DoT) Govt. of India. This project will create a 5G prototype and testing platform that will be developed under the guidance of IIT-H faculty.
The project will deliver an end-to-end 5G testbed comprising 5G BS and UE nodes that support enhanced mobile broadband (eMBB), Ultra low latency communication (URLLC), and massive MTC including NB IoT services. The operating frequently includes both sub 6 GHz and mmwave frequencies. The system will exceed IMT 2020 5G performance requirements including Low Mobility Large Cell (i.e.., LMLC) targets introduced by India at ITU.
The 'Indigenous 5G Testbed' project is a long-term effort with a team of 100+ researchers/engineers based out of IIT-H campus.
About Company
Espressif Systems is a multinational, fabless semiconductor company established in 2008, with headquarters in Shanghai and offices in Greater China, India and Europe. We have a passionate team of engineers and scientists from all over the world, focused on developing cutting-edge WiFi-and-Bluetooth, low-power, IoT solutions. Among our popular products are the ESP8266 and ESP32 series of chips, modules and development boards. Espressif has opened a Technology Center in Pune(Baner), India, which will focus on embedded software engineering and IoT solutions development for our growing customers.
At Espressif, communication, collaboration and innovation are of paramount importance. That's why professionals and engineers from around the world have chosen to further their careers at Espressif Systems. They are passionate and committed to developing innovative products. And they are here to ensure that fast,secure and green IoT technology can be available to all. Come and join Espressif, so that you, too, can partake in Espressif's mission in the IoT industry.
BASIC QUALIFICATIONS
- M.Tech/B. Tech in the field of VLSI/Electronics engineering.
- Proficiency in UVM/SV and C/C++ based functional verification
- Experience in UPF based low power design verification
- Automation skills in PERL and/or TCL and/or Shell*
- Team player, with good problem solving and communication skills.
JOB DESCRIPTION
- Drive functional verification at IP/SoC level using UVM/SV test bench
- Work closely with design team to define comprehensive feature test plans
- Perform functional and code coverage for logic verification sign-off
- Must have worked on ARM/RISC-V CPU based designs
- Must have performed gate level sim at SoC level
- Pre and Post-silicon debug/validation experience will be a plus
INTERPERSONAL SKILLS:
- Energetic, self-motivated
- Pro-active, oriented on execution
- Attentive to details and quality
- Team player
- Good communications and reporting skills

