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Job Responsibilities:

• Assist in the design, development, and maintenance of high-quality Android applications using Java/Kotlin.
• Work with Android Studio to write clean, efficient, and well-documented code.
• Implement and adhere to MVVM (Model-View-ViewModel) architectural patterns to ensure scalable and maintainable applications.
• Utilize Data Binding to streamline UI development and improve code readability.
• Develop user interfaces with a strong understanding of various Layouts (ConstraintLayout, LinearLayout, RelativeLayout, etc.) and responsive design principles.
• Integrate applications with RESTful Webservices using libraries like Retrofit to connect with backend services and handle data efficiently.
• Gain experience in interacting with databases, including basic operations with SQLite Database (Creating, Updating/Querying) for local data storage and understanding of server-side data interaction.
• Apply Debugging Skills using tools such as Logcat, Android Debugger (Debug), and Lint for identifying and resolving issues, and optimizing application performance.
• Leverage Plugin Tools like ADB Idea, Codata, and Lombok Plugin (if applicable) to enhance development workflow and productivity.
• Work with various Android APIs to implement new features and functionality.
• Participate in Testing the Android Application, including unit testing and collaborating with QA for functional and integration testing.
• Perform Lint for Code Inspection to ensure code quality, consistency, and adherence to best practices.
• Learn and apply fundamental Design Patterns (e.g., Singleton, Observer) in Android development.
• Collaborate effectively with cross-functional teams, including product managers, UI/UX designers, and backend developers, to define, design, and ship new features.
• Continuously discover, evaluate, and implement new technologies to maximize development efficiency and improve application performance.
• Stay up-to-date with the latest Android development trends and best practices.

Required Skills and Qualifications:

• Bachelor's degree in Computer Science, Information Technology, or a related field (or equivalent practical experience).
• 0-2 years of hands-on experience in Android application development.
• Solid understanding of Android SDK and Android Studio.
• Proficiency in at least one of the primary Android programming languages: Java or Kotlin.
• Familiarity with MVVM architecture.
• Basic knowledge of Data Binding.
• Understanding of various Android Layouts.
• Exposure to SQLite Database and concepts of server-side interaction.
• Familiarity with Retrofit for API consumption.
• Demonstrated Debugging Skills using relevant Android tools.
• Awareness of common Plugin Tools for Android development.
• Basic understanding of Android APIs.
• Knowledge of RESTful Webservices principles.
• Experience with testing methodologies for Android applications.
• Ability to use Lint for Code Inspection.
• Eagerness to learn and apply Design Patterns.
• Strong problem-solving abilities and attention to detail.
• Excellent communication and teamwork skills.
• A portfolio of personal or academic Android projects is a strong plus.

Are you a motivated and knowledgeable engineer ready to make a significant impact in the world of advanced technology? Designnex is on the lookout for a dynamic Design Verification Engineer to join our innovative team. In this exciting role, you will collaborate closely with customers to verify cutting-edge Interface IP (IIP) in their ASIC SoC/systems for groundbreaking next-generation products.

Key Responsibilities:

• Collaborate with customers to verify cutting-edge IPs in their ASIC SoC/systems.
• Provide support throughout the ASIC design cycle, focusing on design verification.
• Engage with the latest industry specifications and applications.
• Work with a diverse, worldwide team and interact with industry experts and leaders.

Key Qualifications:

• Experience: At least 2 years of related ASIC design verification experience. Strong academic backgrounds with relevant knowledge considered.

Skills:

• Experience in IP design verification flow of ASIC/SoC design (e.g., simulation, verification, RTL synthesis).
• Advanced lab experience (e.g., ATE, high-speed interface IP bring-up).
• Strong communication skills and ability to interact with peers from different geographies.
• Proficiency in UVM and SystemVerilog.
• Good to Know: PCIE and CXL specifications and design verification.

Preferred Experience:

• Technical knowledge of Interface IPs such as PCIe, Ethernet Protocols, Specification, Design, Verification, and Implementation.
• Proven track record in meeting tight schedules and handling multiple projects concurrently.
• Experience in various ASIC design cycles, including HIP/SIP integration into high-scale SoCs, design verification flows, physical implementation, SI/PI, and silicon bring-up in the lab.

Join Designnex and be part of a team at the forefront of technological advancements. Apply today and help shape the future of ASIC design and integration!

Job Description :

Own partition floorplanning for optimizing blocks for Power, Performance and Area.

Own execution from synthesis to place and route of partitions through all signoff including timing signoff, physical verification, EMIR signoff , Formal Equivalence, and Low Power Verification.

Have close collaboration with RTL team to help drive and resolve design issues related to block closure.

Understand tools, flows, and overall design methodology in design construction, signoff, and optimization with a data driven approach.

Implement robust clock distribution solutions using appropriate methods that meet design requirements.

Make good independent technical trade-offs between power, area, and timing (PPA)

Responsibilities

 Develop an effective test suite based on the FPGA requirements.

 Testbench architecture with System Verilog and UVM

 Develop test environments based on the architecture.

 Develop Agents, Drivers, Monitors, Predictors, Scoreboard, and Sequences etc.

 Actively participate in a team environment, working with verification,

architecture, applications, and design teams to develop comprehensive

verification plans and address issues.

 Verification environment development/update for block level and system level.

 Own and drive verification related activities, provide technical support, and

proactively manage tasks to meet schedule goals.

 Define and develop effective functional assertions and coverpoints

 Debug the design issues and report through appropriate tools

 Code Coverage analysis and test case identification for improving the code

coverage.

 Perform timing simulations.

 Apply techniques and skills required to identify a root cause of a given issue and

very good debugging skills.

 Technical guidance to the junior engineers on verification tasks.

Qualifications

 Bachelor's/Master's degree in Engineering (Electronics and Communication or

VLSI )

 10+ years of Industry experience in development, integration & verification of

ASIC/FPGA.

 Protocols – PCIe, SPI, ARINC 429, Mil 1553, Image processing or similar.

 Hands on experience in developing System Verilog/UVM verification

environment from scratch.

 Hands on experience with Questa or similar advanced simulation tools.

 Hands on experience in DO-254 verification process.

 Experience in DOORS/Jama will be a plus.

 Experience in Video domain will be a plus.

StartUp engaged in inventing and innovating Smart Energy Meters and related Technologies (OEM) requires Embedded Engineers. Following re-innovation principle and Technology First direction, we design Technologies to deliver our Vision of the highest Quality Products and Technologies. The candidate's responsibilities include IoT (COSEM/DLMS), technology integration. Required skills include Embedded C and C++ and knowledge of Electrical and Electronics.

Job Title: Project Associate - Mixed Signal Design Profile
Industry: Wireless communication, 5G
Organization: 5G TestBed-IIT Hyderabad- Hyderabad

Job Description
Work Profile:
· Work on development of custom Analog circuit boards for applications related to RF, interfaces etc.
· Implement new features and bug fixes
· Verify analog/mixed-signal integrated circuits
· Develop test cases to verify new features and bug fixes
· Review and update the user manuals for software tools.
· Supporting digital modelling of analog circuits for mixed-signal verification
· Creating design specifications and circuit schematics
· Work both independently and in a team environment, with the opportunity to provide technical leadership to other members of the engineering team
· Create and/or modify specification documents detailing system design and enhancements to meet marketing requirements
· Collaborate with others in the creation of technical reports, whitepapers, and user documentation

Requisites:
· EE/EEE/ECE graduate, undergraduate degree from reputed Tier 1 or Tier 2 colleges .
· Strong knowledge of analog integrated circuit design fundamentals
· Proven experience taking designs from concept to production
· Experience in analog/mixed-signal IC design & verification
· Understanding of BJT, CMOS and Op-Amp technologies.
· Good understanding of analog/mixed-signal design flows (Cadence, Synopsys)
· Transistor and system level simulation skills
· Discrete time and continuous time signal processing skills
· Strong lab and silicon validation skills
· Verilog based digital design and test bench development, is a plus
· Strong communication skills, both written and verbal
About us:
For more details please visit: http://5g.iith.ac.in/
IIT Hyderabad in collaboration with top Indian institutes including IITM, CEWiT, IITD, IITK, IISC and SAMEER is building the largest 5G testbed of the country, with the support of Department of Telecommunications (DoT) Govt. of India. This project will create a 5G prototype and testing platform that will be developed under the guidance of IIT-H faculty.
The project will deliver an end-to-end 5G testbed comprising 5G BS and UE nodes that support enhanced mobile broadband (eMBB), Ultra low latency communication (URLLC), and massive MTC including NB IoT services. The operating frequently includes both sub 6 GHz and mmwave frequencies. The system will exceed IMT 2020 5G performance requirements including Low Mobility Large Cell (i.e.., LMLC) targets introduced by India at ITU.
The 'Indigenous 5G Testbed' project is a long-term effort with a team of 100+ researchers/engineers based out of IIT-H campus.

About Company

Espressif Systems is a multinational, fabless semiconductor company established in 2008, with headquarters in Shanghai and offices in Greater China, India and Europe. We have a passionate team of engineers and scientists from all over the world, focused on developing cutting-edge WiFi-and-Bluetooth, low-power, IoT solutions. Among our popular products are the ESP8266 and ESP32 series of chips, modules and development boards. Espressif has opened a Technology Center in Pune(Baner), India, which will focus on embedded software engineering and IoT solutions development for our growing customers.

At Espressif, communication, collaboration and innovation are of paramount importance. That's why professionals and engineers from around the world have chosen to further their careers at Espressif Systems. They are passionate and committed to developing innovative products. And they are here to ensure that fast,secure and green IoT technology can be available to all. Come and join Espressif, so that you, too, can partake in Espressif's mission in the IoT industry.

BASIC QUALIFICATIONS

• M.Tech/B. Tech in the field of VLSI/Electronics engineering. 
• Proficiency in UVM/SV and C/C++ based functional verification 
• Experience in UPF based low power design verification
• Automation skills in PERL and/or TCL and/or Shell* 
• Team player, with good problem solving and communication skills. 

JOB DESCRIPTION 

• Drive functional verification at IP/SoC level using UVM/SV test bench
• Work closely with design team to define comprehensive feature test plans
• Perform functional and code coverage for logic verification sign-off
• Must have worked on ARM/RISC-V CPU based designs
• Must have performed gate level sim at SoC level
• Pre and Post-silicon debug/validation experience will be a plus

INTERPERSONAL SKILLS:

• Energetic, self-motivated
• Pro-active, oriented on execution
• Attentive to details and quality
• Team player
• Good communications and reporting skills