7+ EMIR Jobs in India
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Job Description :
Own partition floorplanning for optimizing blocks for Power, Performance and Area.
Own execution from synthesis to place and route of partitions through all signoff including timing signoff, physical verification, EMIR signoff , Formal Equivalence, and Low Power Verification.
Have close collaboration with RTL team to help drive and resolve design issues related to block closure.
Understand tools, flows, and overall design methodology in design construction, signoff, and optimization with a data driven approach.
Implement robust clock distribution solutions using appropriate methods that meet design requirements.
Make good independent technical trade-offs between power, area, and timing (PPA)
Responsibilities will include, but are not limited to:
- Contribute to new Memory based product opportunities by assisting with the overall design, layout, and optimization of Memory/Logic circuits
- Responsible to translate system-level specs onto the circuit block-level performance spec, circuit architecture, design and development
- Perform verification processes with modeling and simulation using industry-standard simulators
- Document and review final results
- Chip in to cross-group communication to work towards standardization and group success
- Actively solicit guidance from Standards, CAD, modeling, and verification groups to ensure the design quality
Successful candidates for this position will have:
- A Bachelor's or Master's degree (Preferred) in Electrical Engineering, Computer Engineering, or related discipline
- Proven knowledge of CMOS Circuit Design
- Experience in RTL design, design synthesis, static timing analysis, and automated layout techniques
- Hands-on experience with Verilog modeling and simulation tools
- Knowledge of state machine logic/design verification techniques
- Excellent problem-solving and analytical skills
- Experience with a scripting language (Python, Tcl, Perl, etc)
FPGA Physical Layer Developer for 5G-NR
Experience: 2 years to 6 years
Skill:
FPGA IP Blocks integration using Xilinx Vivado Platform
Knowledge on AXI Protocols
Xilinx PS-PL integration knowledge
RTL Programming: Verilog
FPGA Test Bench Development using Xilinx Vivado
L1/Physical Layer Implementation on Xilinx FPGA (RFSoC)
FPGA Debugging Tools Experience: ILA, chipscope, VIO
Working knowledge of the following engineering tools: Xilinx Vivado, Xilinx ISE/EDK
FPGA Modem/Communication Blocks development/testing experience regarding 4G/5G
or any wireless standard will be preferred
M.Tech. in VLSI will be preferred
Good Academic Score
InnoPhase Bangalore is looking for a Senior Engineer, Digital Physical Design to join a growing start
up semiconductor development organization and to help drive excellence in our IoT products.
Roles & Responsibilities
Design, Develop and execute physical design implementation of low-power and high-performance SoC, including
logic synthesis, floorplan and power plan, power domain specification, place and route, clock tree synthesis, static
timing analysis, IR drop analysis, EM, and physical verification in advanced technology nodes.
- Work with the RTL and System design teams to drive the physical design of the device in the early design cycle.
- Design, implement and verify suitable methodology that meets the QoR goals.
- Resolve design and flow issues related to the physical design, identify potential solutions, and drive
- Deliver physical design of entire SoC, complete with specification, flow and automation.
- Interface with the RTL design team to drive design modifications to resolve physical design issues and
- Use EDA tool-based programming and scripting techniques to automate and improve throughput and quality.
- Interact with tool vendors to drive tool fixes and flow improvements. Perform tool evaluations of new
Desired Qualities
- Bachelor’s degree (Master’s preferred) in Electrical Engineering or comparable engineering discipline.
- 5 to 8 years of relevant experience is required.
- Experience in physical design and timing closure for advanced nodes.
- Experience in Cadence EDA tools for physical design and verification.
- Experience in floor planning, power planning, CTS specification, place & route, and timing closure.
- Experience in UPF specs design and implementation.
- Be able to work with cross-functional teams, IP, and EDA vendors
Skills/Experience
Experience with complete flows involving timing closure of high speed digital design using scripting languages and design automation.
Has deep knowledge of Xilinx FPGA implementation and tools.
Experience in state of the art tools and flows.
Working knowledge in Verilog and System Verilog.
Job Requirements
Bachelors in Electronics Engineering.
Strong knowledge of ASIC and/or FPGA design methodology and should be well versed in front-end design, simulation, and verification CAD tools.
Relevant FPGA/ASIC engineering design and verification experience is entertained.
Excellent verbal, written and communication skills are required.
Excellent follow-through, motivation, and persistence
Strong technical judgment and decision making abilities.
Knowledge of digital board design and signal integrity principles is a plus.
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