4+ Synopsys Jobs in India

Job Title: Sr Dev Ops Engineer

Location: Bengaluru- India (Hybrid work type)

Reports to: Sr Engineer manager

About Our Client : 

We are a solution-based, fast-paced tech company with a team that thrives on collaboration and innovative thinking. Our Client's IoT solutions provide real-time visibility and actionable insights for logistics and supply chain management. Cloud-based, AI-enhanced metrics coupled with patented hardware optimize processes, inform strategic decision making and enable intelligent supply chains without the costly infrastructure

About the role : We're looking for a passionate DevOps Engineer to optimize our software delivery and infrastructure. You'll build and maintain CI/CD pipelines for our microservices, automate infrastructure, and ensure our systems are reliable, scalable, and secure. If you thrive on enhancing performance and fostering operational excellence, this role is for you. 

What You'll Do 🛠️

• Cloud Platform Management: Administer and optimize AWS resources, ensuring efficient billing and cost management.
• Billing & Cost Optimization: Monitor and optimize cloud spending.
• Containerization & Orchestration: Deploy and manage applications and orchestrate them.
• Database Management: Deploy, manage, and optimize database instances and their lifecycles.
• Authentication Solutions: Implement and manage authentication systems.
• Backup & Recovery: Implement robust backup and disaster recovery strategies, for Kubernetes cluster and database backups.
• Monitoring & Alerting: Set up and maintain robust systems using tools for application and infrastructure health and integrate with billing dashboards.
• Automation & Scripting: Automate repetitive tasks and infrastructure provisioning.
• Security & Reliability: Implement best practices and ensure system performance and security across all deployments.
• Collaboration & Support: Work closely with development teams, providing DevOps expertise and support for their various application stacks. 

What You'll Bring 💼

• Minimum of 4 years of experience in a DevOps or SRE role.
• Strong proficiency in AWS Cloud, including services like Lambda, IoT Core, ElastiCache, CloudFront, and S3.
• Solid understanding of Linux fundamentals and command-line tools.
• Extensive experience with CI/CD tools, GitLab CI.
• Hands-on experience with Docker and Kubernetes, specifically AWS EKS.
• Proven experience deploying and managing microservices.
• Expertise in database deployment, optimization, and lifecycle management (MongoDB, PostgreSQL, and Redis).
• Experience with Identity and Access management solutions like Keycloak.
• Experience implementing backup and recovery solutions.
• Familiarity with optimizing scaling, ideally with Karpenter.
• Proficiency in scripting (Python, Bash).
• Experience with monitoring tools such as Prometheus, Grafana, AWS CloudWatch, Elastic Stack.
• Excellent problem-solving and communication skills. 

Bonus Points ➕

• Basic understanding of MQTT or general IoT concepts and protocols.
• Direct experience optimizing React.js (Next.js), Node.js (Express.js, Nest.js) or Python (Flask) deployments in a containerized environment.
• Knowledge of specific AWS services relevant to application stacks.
• Contributions to open-source projects related to Kubernetes, MongoDB, or any of the mentioned frameworks.
• AWS Certifications (AWS Certified DevOps Engineer, AWS Certified Solutions Architect, AWS Certified SysOps Administrator, AWS Certified Advanced Networking).

Why this role: 

•You will help build the company from the ground up—shaping our culture and having an impact from Day 1 as part of the foundational team.

Job Title : Hardware Design Developer – Verilog

Employment Type : Full-Time Contract (8 hours/day)

Location : Remote

Experience : 3+ Years (Mandatory)

Notice Period : Immediate

Job Overview :

We are looking for an experienced Hardware Design Developer to leverage hardware design platforms for generating training data to enhance enterprise LLMs' capabilities. This role offers a unique opportunity to directly impact AI advancements by optimizing hardware designs for training and benchmarking large language models.

Key Responsibilities :

• Develop, configure, and customize hardware design platforms to generate training data for enterprise LLMs.
• Work closely with research teams to translate requirements into actionable insights.
• Ensure high-quality coding, debugging, and documentation to optimize hardware design solutions.
• Collaborate with cross-functional teams to improve LLM performance and automation capabilities.

Required Skills & Experience:

• BS/MS in Electrical Engineering or related field.
• 3 to 5 Years of hardware design development experience.
• Expertise in HDLs (Verilog, SystemVerilog, VHDL, SystemC).
• Strong background in scripting, front-end workflows, and verification processes.
• Familiarity with Synopsys, Cadence, or open-source toolchains.
• Excellent problem-solving and collaboration skills.

Preferred Qualifications :

• Expertise in UVM environments, Formal Verification, and Lint refinement.
• Experience with Computer Architecture, Assembly Debugging, and Assertion Coding (SVA).
• Familiarity with Machine Learning and AI systems.

Mandatory Technical Skills :

• Min 2 Years of relevant experience in Hardware Design and/or Verification.
• Experience with at least one of the following:
• ASIC, VLSI, FPGA, SoC development.
• SystemVerilog, Verilog, Testbench development, and Verification.
• Strong understanding of IP Development and Verification.

Note: This role focuses on LLM training using hardware design, not traditional project development.

Physical Design - JD

Experience: 2-20 yrs
1.Strong background of ASIC Physical Design: Floor planning, P&R, Extraction, IR Drop Analysis, Static Timing and Signal Integrity.                          
2.Hands-on experience on technology nodes like 7nm, 14nm, 10nm.
3.Good knowledge of EDA tools from Synopsys , Cadence and Mentor              
4.Hands-on experience in floor planning, placement optimizations, CTS and routing.                                  
5.Hands-on experience in cadence or Synopsys tool (Encounter, ICC, PT/PTSI, TEMPUS, DC, RC, VOLTAS)

Dear Connections,

Roles & Responsibility:-
Should execute block level floor planning, PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks.

Physical Design Implementation on advanced technology nodes like 28nm, 20nm for block level implementation. Good understanding on low power concepts. Good understanding on top level physical design, partitioning and timing constraints, IR Drop.

Candidate should be from semiconductor/'ASIC industry
Excellent knowledge on GDS To Netlift