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About the organization

QFocus AI Pvt. Ltd. (QFAI), a wholly owned subsidiary of QFocus Technologies LLC, is a consulting-led engineering services company with sharp focus on supporting next gen advanced products development across AI/ML, Compute, Communication, Storage and Consumer Electronics. Our mission is to help our customers deliver cutting-edge products on time ensuring world-class quality.

Why Join QFAI? Join a passionate team, dedicated to making a difference.  

We are a close-knit team, with strong mission, vision and values that guide our day-to-day.  Recognition of work, respect, and our multicultural community are key aspects of the employee experience and contribute to our continued success.  Would you like to be part of our story? Don't hesitate, come and join us! 

About this opportunity – Formal Verification Engineer

We are seeking a highly skilled and passionate Formal Verification Engineer to join our team working with the best in the Industry, developing innovative ASIC solutions for data center and AI Infrastructure. The ideal candidate will develop comprehensive formal test plans and be responsible for complete formal verification sign-off of single or multiple complex blocks. The role also provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC Design, Emulation and Post-Silicon teams towards creating a first-pass silicon success.

Key Responsibilities:

·      Contribute to Formal Verification applying and evangelizing state of the art Formal Verification Methodologies across IP-level, subsystem-level and SOC Level.

·      Collaborate with Architecture and Design teams to develop formal specifications and implementations.

·      Define formal verification scope, create formal environments, and achieve coverage sign-off using targeted formal verification techniques.

·      Develop comprehensive formal test plans, including unique security requirement verification.

·      Build reusable and scalable formal verification environments and deploy relevant tools.

·      Evaluate and recommend EDA solutions for Formal Verification and drive improvements to methodologies and flows.

·      Debug complex issues in RTL designs based on formal results and contribute to design improvements.

Required Skills:

1. Strong hands-on experience with Formal Verification tools (e.g., JasperGold, VC-Formal, Questa Formal).
2. Experience writing formal properties using System Verilog Assertions (SVA) or Property Specification Language (PSL).
3. Proven understanding of Formal Verification methodologies, complexity reduction techniques, and abstraction techniques.
4. Fluency in hardware description languages, such as SystemVerilog.
5. Proficiency in scripting languages such as Python, Perl, or Tcl within Unix/Linux environments.

 Education:

Bachelor's degree in Computer Science, Computer Engineering, Electrical Engineering, or a related technical field, or equivalent practical experience.

Experience:

5+ years of experience in Design Verification, with at least 1 year in Formal Verification.

QFocus AI Pvt Ltd is an Equal Employment Opportunity employer.

Physical Design - JD

Experience: 2-20 yrs
1.Strong background of ASIC Physical Design: Floor planning, P&R, Extraction, IR Drop Analysis, Static Timing and Signal Integrity.                          
2.Hands-on experience on technology nodes like 7nm, 14nm, 10nm.
3.Good knowledge of EDA tools from Synopsys , Cadence and Mentor              
4.Hands-on experience in floor planning, placement optimizations, CTS and routing.                                  
5.Hands-on experience in cadence or Synopsys tool (Encounter, ICC, PT/PTSI, TEMPUS, DC, RC, VOLTAS)

Dear Connections,

Roles & Responsibility:-
Should execute block level floor planning, PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks.

Physical Design Implementation on advanced technology nodes like 28nm, 20nm for block level implementation. Good understanding on low power concepts. Good understanding on top level physical design, partitioning and timing constraints, IR Drop.

Candidate should be from semiconductor/'ASIC industry
Excellent knowledge on GDS To Netlift