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We are seeking a highly skilled and passionate Hardware Emulation Engineer to join our team working withthe best in the Industry, developing innovative ASIC solutions for data center and AI Infrastructure. As an Hardware Emulation Engineer, you will be at the forefront of pre-silicon validation, ensuring the highest quality and functionality of our hardware before it goes into production.

Key Responsibilities:

·      Emulation Environment Development: Build and maintain pre-silicon emulation platforms using industry-standard systems such as Cadence Palladium or Synopsys ZeBu or Veloce Strato, Primo

·      Model Integration and Optimization: Integrate the RTL design onto the emulation platform by ensuring synthesizability, optimize build efficiency and performance, and work with high-performance transactors and emulation testbenches (e.g., using SystemVerilog, C/C++, Python).

·      Flush out emulation flow issues by performing smoke verification

·      Support validation team in execute comprehensive test content, including bare-metal and OS-based tests, to accelerate bug finding in pre-silicon on the emulation platform.

·      Collaboration: Work closely with cross-functional teams including design, verification and SW development teams to understand issues in using the emulation platform.

·      Flow Automation: Develop and enhance automation scripts and flows using Python, Perl, and shell scripting to manage regressions, optimize runtime, and improve overall verification efficiency.

·      Vendor Collaboration: Interface with emulation platform vendors to debug and quickly resolve technical issues encountered with the tools.

·      The candidate must be able to work independently and proactively on allocated technical tasks.

Required Skills:

·      Proficiency in Hardware Description Languages (HDLs) such as Verilog and SystemVerilog.

·      SoC Knowledge: Solid understanding of SoC architectures and industry-standard protocols (e.g. AXI, PCIe, ETH, USB, HVM)

·      Experience with verification methodologies (UVM, SVA) and related verification environments, including C/C++ DPI is desirable.

·      Strong scripting skills in Python, Perl, Tcl, or Shell for automation.

·      Familiarity with debugging tools (e.g., Verdi, SimVision) and waveform analysis is desirable.

Education:

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.

Experience:

·      Proven experience of 5+ years in hardware verification and/or emulation roles.

·      Hands-on experience with at least one of the major commercial emulation platforms (Cadence Palladium, Synopsys ZeBu, or Siemens Veloce).

QFocus AI Pvt Ltd is an Equal Employment Opportunity employer.

Physical Design - JD

Experience: 2-20 yrs
1.Strong background of ASIC Physical Design: Floor planning, P&R, Extraction, IR Drop Analysis, Static Timing and Signal Integrity.                          
2.Hands-on experience on technology nodes like 7nm, 14nm, 10nm.
3.Good knowledge of EDA tools from Synopsys , Cadence and Mentor              
4.Hands-on experience in floor planning, placement optimizations, CTS and routing.                                  
5.Hands-on experience in cadence or Synopsys tool (Encounter, ICC, PT/PTSI, TEMPUS, DC, RC, VOLTAS)

Dear Connections,

Roles & Responsibility:-
Should execute block level floor planning, PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks.

Physical Design Implementation on advanced technology nodes like 28nm, 20nm for block level implementation. Good understanding on low power concepts. Good understanding on top level physical design, partitioning and timing constraints, IR Drop.

Candidate should be from semiconductor/'ASIC industry
Excellent knowledge on GDS To Netlift