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(INDIA) BANGALORE, INDIA /
ENGINEERING – SILICON ENGINEERING /
Join a well funded startup as an analog engineer leading the designs for droop sensing, clocking, PLL, LDO, On-die VRs and PMICs using latest finfet technology nodes. Our mission is to reimagine silicon and disrupt the high performance computing platforms with the RiscV based chiplet designs.
- Responsible for design and spec development and design of analog blocks for advanced mixed-signal / analog circuits.
- Write detailed design specification and will be in close collaboration with the system architect, circuit designers and design verification engineers.
- Work on behavioral modeling of analog blocks and support design verification to ensure bug free silicon.
- Lead development of analog blocks in collaboration with external vendors and lead integration, test plan and characterization efforts.
- Strong track record of architect, develop, verification and validation of complete silicon IPs
- Deep understanding of bandgaps, bias, opamps, switched-cap circuits, LDOs, PLLs, feedback and compensation techniques, DCDC converters
- In-depth knowledge and good understanding of analog design techniques.
- Experience in digital integration of analog IPs with chip level integration team
- Experience in developing behavior modeling a plus
- Experience IP design management or vendor management a plus
- Strong device physics knowledge as it applies to analog IC design
- Hand-on experience with IP lab characterization using spectrum analyzers, oscilloscopes, signal generators, etc.
- Experience in working with production test engineers to produce test plans and design for testability details
- Excellent communication skills
- Team player with an ability to encourage team members
Education & Experience
- MS (preferred in EE) plus 8 years
- PhD (preferred in EE) plus 5 years
Annual job salary: The annual job salary mentioned in this posting is a default number taken by cutshort and is inaccurate.
Interested folks with 3+ years to 20 years of experience into AMS Design, Please reach out to the Recruiter Deepa Savant to learn more about the job and discuss details.
JD for Circuit design:
- Design CMOS/FinFet-based analog and mixed-signal integrated circuits independently / under the supervision of a lead engineer.
- Hands-on experience with min. 2-3 analog circuit design IP from SPEC to final GDS delivery.
- Support analog/mixed-signal IP validation from pre-layout, post-layout till post-tape out phase
- Hands-on with state-of-the-art CAD tools and flows required for simulation, verification, and reliability checks.
- Knowledge of layout issues; especially in FinFet nodes
- Document design ideas and simulation results as per SPEC/design guidelines
- 3-6+ years of industry experience in the area of mixed-signal CMOS circuit design
- Able to create new analog behavioral models (WREAL / Verilog AMS) and/or update existing ones
- Experience with System Verilog and UVM Methodology
- Innovative and creative thinker
- Ability to quickly ramp up on new projects
- Working knowledge of PERL, TCL and UNIX shell scripting language
alog Circuit Design::
- The candidate should have B.Tech or M.Tech in Electronics/Electrical/VLSI Design Engineering
- The candidate should have relevant work experience of 7-16 years in Analog and SERDES IO IP design e.g. GPIOs, Thermal Sensor, PLL, ADC/DAC/ Voltage regulators/LDOs, AIB, HBMIO, DDR, HDMI/DP IO, MIPI IO etc.
Experience : 4-8 year digital/analog circuit design experience • Transistor level electrical circuit design required • Transistor level physical circuit design a plus • Experience with Cadence Tools • Familiar with PDK - Ground Rule, Layout versus Schematic, and Methodology Checking Tools • Familiarity with Extraction tools (Synopsys StarRC or Cadence Quantus QRC) • Deep understanding of Cadence Spectre or Equivalent Circuit Simulation and Analysis Tools
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