
Review Criteria
- Strong Dremio / Lakehouse Data Architect profile
- 5+ years of experience in Data Architecture / Data Engineering, with minimum 3+ years hands-on in Dremio
- Strong expertise in SQL optimization, data modeling, query performance tuning, and designing analytical schemas for large-scale systems
- Deep experience with cloud object storage (S3 / ADLS / GCS) and file formats such as Parquet, Delta, Iceberg along with distributed query planning concepts
- Hands-on experience integrating data via APIs, JDBC, Delta/Parquet, object storage, and coordinating with data engineering pipelines (Airflow, DBT, Kafka, Spark, etc.)
- Proven experience designing and implementing lakehouse architecture including ingestion, curation, semantic modeling, reflections/caching optimization, and enabling governed analytics
- Strong understanding of data governance, lineage, RBAC-based access control, and enterprise security best practices
- Excellent communication skills with ability to work closely with BI, data science, and engineering teams; strong documentation discipline
- Candidates must come from enterprise data modernization, cloud-native, or analytics-driven companies
Preferred
- Preferred (Nice-to-have) – Experience integrating Dremio with BI tools (Tableau, Power BI, Looker) or data catalogs (Collibra, Alation, Purview); familiarity with Snowflake, Databricks, or BigQuery environments
Job Specific Criteria
- CV Attachment is mandatory
- How many years of experience you have with Dremio?
- Which is your preferred job location (Mumbai / Bengaluru / Hyderabad / Gurgaon)?
- Are you okay with 3 Days WFO?
- Virtual Interview requires video to be on, are you okay with it?
Role & Responsibilities
You will be responsible for architecting, implementing, and optimizing Dremio-based data lakehouse environments integrated with cloud storage, BI, and data engineering ecosystems. The role requires a strong balance of architecture design, data modeling, query optimization, and governance enablement in large-scale analytical environments.
- Design and implement Dremio lakehouse architecture on cloud (AWS/Azure/Snowflake/Databricks ecosystem).
- Define data ingestion, curation, and semantic modeling strategies to support analytics and AI workloads.
- Optimize Dremio reflections, caching, and query performance for diverse data consumption patterns.
- Collaborate with data engineering teams to integrate data sources via APIs, JDBC, Delta/Parquet, and object storage layers (S3/ADLS).
- Establish best practices for data security, lineage, and access control aligned with enterprise governance policies.
- Support self-service analytics by enabling governed data products and semantic layers.
- Develop reusable design patterns, documentation, and standards for Dremio deployment, monitoring, and scaling.
- Work closely with BI and data science teams to ensure fast, reliable, and well-modeled access to enterprise data.
Ideal Candidate
- Bachelor’s or master’s in computer science, Information Systems, or related field.
- 5+ years in data architecture and engineering, with 3+ years in Dremio or modern lakehouse platforms.
- Strong expertise in SQL optimization, data modeling, and performance tuning within Dremio or similar query engines (Presto, Trino, Athena).
- Hands-on experience with cloud storage (S3, ADLS, GCS), Parquet/Delta/Iceberg formats, and distributed query planning.
- Knowledge of data integration tools and pipelines (Airflow, DBT, Kafka, Spark, etc.).
- Familiarity with enterprise data governance, metadata management, and role-based access control (RBAC).
- Excellent problem-solving, documentation, and stakeholder communication skills.

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Founded by serial Entrepreneurs, Level Five Cartronics is a fabless semiconductor design company headquartered in Bengaluru, building automotive-grade Power Management ICs (PMICs), high-precision oscillators, and high-performance phase-locked loops (PLLs) for the next generation of vehicle electronics. Our portfolio centres on low-EMI power delivery — including spread-spectrum EMI suppression — and low-jitter clocking and interface solutions for safety-critical solutions and infotainment systems. We design DC-DC converters, LDOs, and clock distribution networks (including low-jitter PCIe Gen 4, 5, and 6 buffers) in CMOS and BCD high-voltage processes across the 55nm, 90nm and 180nm nodes. We own our products end to end, from architecture through silicon characterization and productization, as part of India's growing fabless semiconductor ecosystem.
The Role
We are looking for a hands-on Head of Engineering, based at our Bengaluru headquarters, to lead our analog/mixed-signal design organization. This is a senior leadership position for an engineer who has personally taken complex automotive power, clocking, and high-speed interface products from concept to high-volume production — and who can build, mentor, and scale the cross-functional team that does it again and again.
You will set the technical direction for our PMIC, oscillator, PLL, and PCIe buffer roadmaps, own design quality and tape-out readiness, and partner closely with characterization, product, and test engineering to ensure every product meets stringent automotive reliability, jitter, and EMC requirements.
What You'll Do
1. Lead and grow the analog/mixed-signal design, layout, and verification teams across multiple product lines, based out of our Bengaluru engineering center.
2. Own the technical architecture and execution of automotive-grade PMICs, DC-DC converters, LDOs, low phase noise Fractional-N phase-locked loops (PLLs), and low-jitter PCIe Gen 4, 5, and 6 buffers.
3. Target high-speed interface applications by driving low phase noise PLL architectures explicitly optimized for PCIe Gen 4, 5, and 6 standards.
4. Drive designs across CMOS and BCD high-voltage processes at 55nm, 90nm and 180nm, from specification through tape-out and qualification.
5. Set and enforce design methodology, review gates, and tape-out criteria; review schematics, layout, and verification plans personally where it matters.
6. Partner with characterization engineers on lab bring-up, silicon debug, and correlation of measured results to simulation.
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8. Build and lead cross-functional teams; recruit, develop, and retain top analog and layout talent in India's semiconductor talent market.
9. Be a technical authority and final escalation point for difficult design and silicon issues.
What You'll Bring
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- Experience with PMICs, oscillators, and spread-spectrum / EMI suppression techniques.
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Nice to Have
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- Experience scaling an engineering organization in a fabless environment, ideally within India's semiconductor ecosystem.
Why Level Five Cartronics
You'll own real products in a fast-moving automotive market, work across the full design-to-silicon flow, and shape the engineering culture of a growing fabless company based in Bengaluru — one of India's leading semiconductor design hubs. If you've built power, clocking, and high-speed interface products that ship in cars and you want to lead the team that builds the next ones, we'd like to talk.
Level Five Cartronics is an equal opportunity employer.
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