About Company
Espressif Systems is a multinational, fabless semiconductor company established in 2008, with headquarters in Shanghai and offices in Greater China, India and Europe. We have a passionate team of engineers and scientists from all over the world, focused on developing cutting-edge WiFi-and-Bluetooth, low-power, IoT solutions. Among our popular products are the ESP8266 and ESP32 series of chips, modules and development boards. Espressif has opened a Technology Center in Pune(Baner), India, which will focus on embedded software engineering and IoT solutions development for our growing customers.
At Espressif, communication, collaboration and innovation are of paramount importance. That's why professionals and engineers from around the world have chosen to further their careers at Espressif Systems. They are passionate and committed to developing innovative products. And they are here to ensure that fast,secure and green IoT technology can be available to all. Come and join Espressif, so that you, too, can partake in Espressif's mission in the IoT industry.
BASIC QUALIFICATIONS
- M.Tech/B. Tech in the field of VLSI/Electronics engineering.
- Proficiency in UVM/SV and C/C++ based functional verification
- Experience in UPF based low power design verification
- Automation skills in PERL and/or TCL and/or Shell*
- Team player, with good problem solving and communication skills.
JOB DESCRIPTION
- Drive functional verification at IP/SoC level using UVM/SV test bench
- Work closely with design team to define comprehensive feature test plans
- Perform functional and code coverage for logic verification sign-off
- Must have worked on ARM/RISC-V CPU based designs
- Must have performed gate level sim at SoC level
- Pre and Post-silicon debug/validation experience will be a plus
INTERPERSONAL SKILLS:
- Energetic, self-motivated
- Pro-active, oriented on execution
- Attentive to details and quality
- Team player
- Good communications and reporting skills
Shubham Vishwakarma
Full Stack Developer - Averlon
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PythonMANDATORY CRITERIA:
- Education: B.Tech / M.Tech in ECE / CSE / IT
- Experience: 10–12 years in hardware board design, system hardware engineering, and full product deployment cycles
- Proven expertise in digital, analog, and power electronic circuit analysis & design
- Strong hands-on experience designing boards with SoCs, FPGAs, CPLDs, and MPSoC architectures
- Deep understanding of signal integrity, EMI/EMC, and high-speed design considerations
- Must have successfully completed at least two hardware product development cycles from high-level design to final deployment
- Ability to independently handle schematic design, design analysis (DC drop, SI), and cross-team design reviews
- Experience in sourcing & procurement of electronic components, PCBs, and mechanical parts for embedded/IoT/industrial hardware
- Strong experience in board bring-up, debugging, issue investigation, and cross-functional triage with firmware/software teams
- Expertise in hardware validation, test planning, test execution, equipment selection, debugging, and report preparation
- Proficiency in Cadence Allegro or Altium EDA tools (mandatory)
- Experience coordinating with layout, mechanical, SI, EMC, manufacturing, and supply chain teams
- Strong understanding of manufacturing services, production pricing models, supply chain, and logistics for electronics/electromechanical components
DESCRIPTION:
COMPANY OVERVIEW:
The company is a semiconductor and embedded system design company with a focus on Embedded, Turnkey ASICs, Mixed Signal IP, Semiconductor & Product Engineering and IoT solutions catering to Aerospace & Defence, Consumer Electronics, Automotive, Medical and Networking & Telecommunications.
REQUIRED SKILLS:
- Extensive experience in hardware board designs and towards multiple product field deployment cycles.
- Strong foundation and expertise in analyzing digital, Analog and power electronic circuits.
- Proficient with SoC, FPGAs, CPLD and MPSOC architecture-based board designs.
- Knowledgeable in signal integrity, EMI/EMC concepts for digital and power electronics.
- Completed at least two project from high-level design to final product level deployment.
- Capable of independently managing product’s schematic, design analysis DC Drop, Signal Integrity, and coordinating reviews with peer of layout, mechanical, SI, and EMC teams.
- Sourcing and procurement of electronic components, PCBs, and mechanical parts for cutting-edge IoT, embedded, and industrial product development.
- Experienced in board bring-up, issue investigation, and triage in collaboration with firmware and software teams.
- Skilled in preparing hardware design documentation, validation test planning, identifying necessary test equipment, test development, execution, debugging, and report preparation.
- Effective communication and interpersonal skills for collaborative work with cross-functional teams, including post-silicon bench validation, BIOS, and driver development/QA.
- Hands-on experience with Cadence Allegro/Altium EDA tools is essential.
- Familiarity with programming and scripting languages like Python and Perl, and experience in test automation is advantageous.
- Should have excellent exposure with coordination of Manufacturing Services, pricing model for production value supply chain & Logistics in electronics and electromechanical components domain.
About the organization
QFocus AI Pvt. Ltd. (QFAI), a wholly owned subsidiary of QFocus Technologies LLC, is a consulting-led engineering services company with sharp focus on supporting next gen advanced products development across AI/ML, Compute, Communication, Storage and Consumer Electronics. Our mission is to help our customers deliver cutting-edge products on time ensuring world-class quality.
Why Join QFAI? Join a passionate team, dedicated to making a difference.
We are a close-knit team, with strong mission, vision and values that guide our day-to-day. Recognition of work, respect, and our multicultural community are key aspects of the employee experience and contribute to our continued success. Would you like to be part of our story? Don't hesitate, come and join us!
About this opportunity – Formal Verification Engineer
We are seeking a highly skilled and passionate Formal Verification Engineer to join our team working with the best in the Industry, developing innovative ASIC solutions for data center and AI Infrastructure. The ideal candidate will develop comprehensive formal test plans and be responsible for complete formal verification sign-off of single or multiple complex blocks. The role also provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC Design, Emulation and Post-Silicon teams towards creating a first-pass silicon success.
Key Responsibilities:
· Contribute to Formal Verification applying and evangelizing state of the art Formal Verification Methodologies across IP-level, subsystem-level and SOC Level.
· Collaborate with Architecture and Design teams to develop formal specifications and implementations.
· Define formal verification scope, create formal environments, and achieve coverage sign-off using targeted formal verification techniques.
· Develop comprehensive formal test plans, including unique security requirement verification.
· Build reusable and scalable formal verification environments and deploy relevant tools.
· Evaluate and recommend EDA solutions for Formal Verification and drive improvements to methodologies and flows.
· Debug complex issues in RTL designs based on formal results and contribute to design improvements.
Required Skills:
- Strong hands-on experience with Formal Verification tools (e.g., JasperGold, VC-Formal, Questa Formal).
- Experience writing formal properties using System Verilog Assertions (SVA) or Property Specification Language (PSL).
- Proven understanding of Formal Verification methodologies, complexity reduction techniques, and abstraction techniques.
- Fluency in hardware description languages, such as SystemVerilog.
- Proficiency in scripting languages such as Python, Perl, or Tcl within Unix/Linux environments.
Education:
Bachelor's degree in Computer Science, Computer Engineering, Electrical Engineering, or a related technical field, or equivalent practical experience.
Experience:
5+ years of experience in Design Verification, with at least 1 year in Formal Verification.
QFocus AI Pvt Ltd is an Equal Employment Opportunity employer.
CAre you a motivated and knowledgeable engineer ready to make a significant impact in the world of advanced technology? Designnex is on the lookout for a dynamic Design Verification Engineer to join our innovative team. In this exciting role, you will collaborate closely with customers to verify cutting-edge Interface IP (IIP) in their ASIC SoC/systems for groundbreaking next-generation products.
Key Responsibilities:
- Collaborate with customers to verify cutting-edge IPs in their ASIC SoC/systems.
- Provide support throughout the ASIC design cycle, focusing on design verification.
- Engage with the latest industry specifications and applications.
- Work with a diverse, worldwide team and interact with industry experts and leaders.
Key Qualifications:
- Experience: At least 2 years of related ASIC design verification experience. Strong academic backgrounds with relevant knowledge considered.
Skills:
- Experience in IP design verification flow of ASIC/SoC design (e.g., simulation, verification, RTL synthesis).
- Advanced lab experience (e.g., ATE, high-speed interface IP bring-up).
- Strong communication skills and ability to interact with peers from different geographies.
- Proficiency in UVM and SystemVerilog.
- Good to Know: PCIE and CXL specifications and design verification.
Preferred Experience:
- Technical knowledge of Interface IPs such as PCIe, Ethernet Protocols, Specification, Design, Verification, and Implementation.
- Proven track record in meeting tight schedules and handling multiple projects concurrently.
- Experience in various ASIC design cycles, including HIP/SIP integration into high-scale SoCs, design verification flows, physical implementation, SI/PI, and silicon bring-up in the lab.
Join Designnex and be part of a team at the forefront of technological advancements. Apply today and help shape the future of ASIC design and integration!
* Chip level verification, 𝗦𝗩/𝗨𝗩𝗠 Methodology
* 𝗘𝘁𝗵𝗲𝗿𝗻𝗲𝘁/𝗔𝗫𝗜/𝗣𝗖𝗜𝗘 protocols and seeded
* Exposure to any of these scripting language -perl/bash-shell/python
* Have lots of debugging skills to quickly scan and identify issues in system verilog/Verilog,C-code
* Good in tool usage for simulation (VCS),waveform debug(Verdi)
- Essential Skills and Experience
- Experience in designing and implementing verification environments for complex RTL designs
- Well-versed in the use of hardware verification languages e.g. SystemVerilog or Specman e
- Verification methodologies such as UVM
- Understanding of end-to-end verification processes, from test plan creation through to verification closure
- Ability to quickly understand and apply complex specification detail
- Understanding of the fundamentals of computer architecture, with an emphasis on pipelining, exception handling, memory systems
- Practical experience of working on microprocessor designs
- In-depth understanding of memory protection, memory translation, vector processing in CPUs, exception and interrupt handling.
- Understanding of constrained random stimulus, the goals and general usefulness of different types of coverage in hardware, as well as checking methodologies and behavioral functional models.
- Knowledge of assembly language (preferably Arm), and/or C/C++
- In-depth technical reviewing of others work
Job Title: Project Associate - Mixed Signal Design Profile
Industry: Wireless communication, 5G
Organization: 5G TestBed-IIT Hyderabad- Hyderabad
Job Description
Work Profile:
· Work on development of custom Analog circuit boards for applications related to RF, interfaces etc.
· Implement new features and bug fixes
· Verify analog/mixed-signal integrated circuits
· Develop test cases to verify new features and bug fixes
· Review and update the user manuals for software tools.
· Supporting digital modelling of analog circuits for mixed-signal verification
· Creating design specifications and circuit schematics
· Work both independently and in a team environment, with the opportunity to provide technical leadership to other members of the engineering team
· Create and/or modify specification documents detailing system design and enhancements to meet marketing requirements
· Collaborate with others in the creation of technical reports, whitepapers, and user documentation
Requisites:
· EE/EEE/ECE graduate, undergraduate degree from reputed Tier 1 or Tier 2 colleges .
· Strong knowledge of analog integrated circuit design fundamentals
· Proven experience taking designs from concept to production
· Experience in analog/mixed-signal IC design & verification
· Understanding of BJT, CMOS and Op-Amp technologies.
· Good understanding of analog/mixed-signal design flows (Cadence, Synopsys)
· Transistor and system level simulation skills
· Discrete time and continuous time signal processing skills
· Strong lab and silicon validation skills
· Verilog based digital design and test bench development, is a plus
· Strong communication skills, both written and verbal
About us:
For more details please visit: http://5g.iith.ac.in/
IIT Hyderabad in collaboration with top Indian institutes including IITM, CEWiT, IITD, IITK, IISC and SAMEER is building the largest 5G testbed of the country, with the support of Department of Telecommunications (DoT) Govt. of India. This project will create a 5G prototype and testing platform that will be developed under the guidance of IIT-H faculty.
The project will deliver an end-to-end 5G testbed comprising 5G BS and UE nodes that support enhanced mobile broadband (eMBB), Ultra low latency communication (URLLC), and massive MTC including NB IoT services. The operating frequently includes both sub 6 GHz and mmwave frequencies. The system will exceed IMT 2020 5G performance requirements including Low Mobility Large Cell (i.e.., LMLC) targets introduced by India at ITU.
The 'Indigenous 5G Testbed' project is a long-term effort with a team of 100+ researchers/engineers based out of IIT-H campus.
- Degree : B.E. or M.S. EE/CS/CE
- Methodologies: SV, UVM & OVM
- Areas of Work: Digital Verification (both IP / SOC)
- Protocol : Knowledge of PCIe/DDR/Ethernet/USB is Plus
- Familiar with Bus protocols like AXI, AHB, SPI and I2C
Follow CutshortShubham Vishwakarma
Full Stack Developer - Averlon