About Company
Espressif Systems is a multinational, fabless semiconductor company established in 2008, with headquarters in Shanghai and offices in Greater China, India and Europe. We have a passionate team of engineers and scientists from all over the world, focused on developing cutting-edge WiFi-and-Bluetooth, low-power, IoT solutions. Among our popular products are the ESP8266 and ESP32 series of chips, modules and development boards. Espressif has opened a Technology Center in Pune(Baner), India, which will focus on embedded software engineering and IoT solutions development for our growing customers.
At Espressif, communication, collaboration and innovation are of paramount importance. That's why professionals and engineers from around the world have chosen to further their careers at Espressif Systems. They are passionate and committed to developing innovative products. And they are here to ensure that fast,secure and green IoT technology can be available to all. Come and join Espressif, so that you, too, can partake in Espressif's mission in the IoT industry.
BASIC QUALIFICATIONS
- M.Tech/B. Tech in the field of VLSI/Electronics engineering.
- Proficiency in UVM/SV and C/C++ based functional verification
- Experience in UPF based low power design verification
- Automation skills in PERL and/or TCL and/or Shell*
- Team player, with good problem solving and communication skills.
JOB DESCRIPTION
- Drive functional verification at IP/SoC level using UVM/SV test bench
- Work closely with design team to define comprehensive feature test plans
- Perform functional and code coverage for logic verification sign-off
- Must have worked on ARM/RISC-V CPU based designs
- Must have performed gate level sim at SoC level
- Pre and Post-silicon debug/validation experience will be a plus
INTERPERSONAL SKILLS:
- Energetic, self-motivated
- Pro-active, oriented on execution
- Attentive to details and quality
- Team player
- Good communications and reporting skills
Subodh Popalwar
Software Engineer, Memorres
About Espressif Systems India Pvt Ltd
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- Knowledge on ARM based architectures of 8/16/32 Microcontrollers,UART, ADC, DAC,Ethernet, SPI,CAN,I2C and I2S.
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Qualification - BE/B.Tech (ECE), M.Sc.(Electronics)
Only Defense and Aerospace, Electronics, Semi-Conductors,
(No Automative industry)
AVANTEL LIMITED is a technology driven public limited company with focus on developing innovative wireless communication products and solutions to meet unique requirements of defense, railways, and telecom sectors. The organization is certified against AS 9100D and ISO 9001:2015 standards for Quality Management System. For more details visit www.avantel.in.
Are you a motivated and knowledgeable engineer ready to make a significant impact in the world of advanced technology? Designnex is on the lookout for a dynamic Design Verification Engineer to join our innovative team. In this exciting role, you will collaborate closely with customers to verify cutting-edge Interface IP (IIP) in their ASIC SoC/systems for groundbreaking next-generation products.
Key Responsibilities:
- Collaborate with customers to verify cutting-edge IPs in their ASIC SoC/systems.
- Provide support throughout the ASIC design cycle, focusing on design verification.
- Engage with the latest industry specifications and applications.
- Work with a diverse, worldwide team and interact with industry experts and leaders.
Key Qualifications:
- Experience: At least 2 years of related ASIC design verification experience. Strong academic backgrounds with relevant knowledge considered.
Skills:
- Experience in IP design verification flow of ASIC/SoC design (e.g., simulation, verification, RTL synthesis).
- Advanced lab experience (e.g., ATE, high-speed interface IP bring-up).
- Strong communication skills and ability to interact with peers from different geographies.
- Proficiency in UVM and SystemVerilog.
- Good to Know: PCIE and CXL specifications and design verification.
Preferred Experience:
- Technical knowledge of Interface IPs such as PCIe, Ethernet Protocols, Specification, Design, Verification, and Implementation.
- Proven track record in meeting tight schedules and handling multiple projects concurrently.
- Experience in various ASIC design cycles, including HIP/SIP integration into high-scale SoCs, design verification flows, physical implementation, SI/PI, and silicon bring-up in the lab.
Join Designnex and be part of a team at the forefront of technological advancements. Apply today and help shape the future of ASIC design and integration!
* Chip level verification, 𝗦𝗩/𝗨𝗩𝗠 Methodology
* 𝗘𝘁𝗵𝗲𝗿𝗻𝗲𝘁/𝗔𝗫𝗜/𝗣𝗖𝗜𝗘 protocols and seeded
* Exposure to any of these scripting language -perl/bash-shell/python
* Have lots of debugging skills to quickly scan and identify issues in system verilog/Verilog,C-code
* Good in tool usage for simulation (VCS),waveform debug(Verdi)
C
INNOPHASE is a rapidly growing communications semiconductor startup with headquarters located in San Diego, CA. It is an exciting time to join InnoPhase and work with a brilliant team of engineers to design innovative wireless products and solutions for IoT/5G.
InnoPhase Bangalore is looking for a Senior Design Verification (DV) Engineer to join a growing start up semiconductor development organization and to help drive excellence in our IOT/5G products.
Responsibilities:
- Follow and help define the team's design verification methodology.
- Write bus functional models that drive and monitor stimulus.
- Plans and implements block and integration level scoreboards and checkers to verify functional behavior.
- Experience constructing chip-level System Verilog and UVM test bench environments, writing System Verilog Assertions (SVAs), with embedded software design and test.
- Develop RAL test plan at SOC/IP level and its implementation.
- Write and analyze functional coverage, providing input to block-level milestones.
- Triage regression failures and identify logic bugs, while driving bug closure.
- Debug test cases and report verification results to achieve the expected code/functional coverage goal. Utilize constrained random verification, functional coverage, code coverage and assertions to achieve goals.
Knowledge and Skills Required:
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science or equivalent.
- 5+ years of experience in VLSI design or verification
- Excellent collaboration, teamwork and communication skills
- Significant experience in reviewing and modifying IP block verification plans, a real plus if created such plans in collaboration with design engineering.
- Track record of completing IP block verification to acceptable coverage metrics.
- Excellent debugging skills, with experience debugging RTL in the block and/or chip-level environments.
- Working knowledge of OVM or UVM methodologies.
- Good analytical and problem-solving skills.
- Proficient knowledge of programming and scripting, hardware description language, electronic design automation (EDA), and/or FPGA tools.
- Essential Skills and Experience
- Experience in designing and implementing verification environments for complex RTL designs
- Well-versed in the use of hardware verification languages e.g. SystemVerilog or Specman e
- Verification methodologies such as UVM
- Understanding of end-to-end verification processes, from test plan creation through to verification closure
- Ability to quickly understand and apply complex specification detail
- Understanding of the fundamentals of computer architecture, with an emphasis on pipelining, exception handling, memory systems
- Practical experience of working on microprocessor designs
- In-depth understanding of memory protection, memory translation, vector processing in CPUs, exception and interrupt handling.
- Understanding of constrained random stimulus, the goals and general usefulness of different types of coverage in hardware, as well as checking methodologies and behavioral functional models.
- Knowledge of assembly language (preferably Arm), and/or C/C++
- In-depth technical reviewing of others work
Job Title: Project Associate - Mixed Signal Design Profile
Industry: Wireless communication, 5G
Organization: 5G TestBed-IIT Hyderabad- Hyderabad
Job Description
Work Profile:
· Work on development of custom Analog circuit boards for applications related to RF, interfaces etc.
· Implement new features and bug fixes
· Verify analog/mixed-signal integrated circuits
· Develop test cases to verify new features and bug fixes
· Review and update the user manuals for software tools.
· Supporting digital modelling of analog circuits for mixed-signal verification
· Creating design specifications and circuit schematics
· Work both independently and in a team environment, with the opportunity to provide technical leadership to other members of the engineering team
· Create and/or modify specification documents detailing system design and enhancements to meet marketing requirements
· Collaborate with others in the creation of technical reports, whitepapers, and user documentation
Requisites:
· EE/EEE/ECE graduate, undergraduate degree from reputed Tier 1 or Tier 2 colleges .
· Strong knowledge of analog integrated circuit design fundamentals
· Proven experience taking designs from concept to production
· Experience in analog/mixed-signal IC design & verification
· Understanding of BJT, CMOS and Op-Amp technologies.
· Good understanding of analog/mixed-signal design flows (Cadence, Synopsys)
· Transistor and system level simulation skills
· Discrete time and continuous time signal processing skills
· Strong lab and silicon validation skills
· Verilog based digital design and test bench development, is a plus
· Strong communication skills, both written and verbal
About us:
For more details please visit: http://5g.iith.ac.in/
IIT Hyderabad in collaboration with top Indian institutes including IITM, CEWiT, IITD, IITK, IISC and SAMEER is building the largest 5G testbed of the country, with the support of Department of Telecommunications (DoT) Govt. of India. This project will create a 5G prototype and testing platform that will be developed under the guidance of IIT-H faculty.
The project will deliver an end-to-end 5G testbed comprising 5G BS and UE nodes that support enhanced mobile broadband (eMBB), Ultra low latency communication (URLLC), and massive MTC including NB IoT services. The operating frequently includes both sub 6 GHz and mmwave frequencies. The system will exceed IMT 2020 5G performance requirements including Low Mobility Large Cell (i.e.., LMLC) targets introduced by India at ITU.
The 'Indigenous 5G Testbed' project is a long-term effort with a team of 100+ researchers/engineers based out of IIT-H campus.
- Degree : B.E. or M.S. EE/CS/CE
- Methodologies: SV, UVM & OVM
- Areas of Work: Digital Verification (both IP / SOC)
- Protocol : Knowledge of PCIe/DDR/Ethernet/USB is Plus
- Familiar with Bus protocols like AXI, AHB, SPI and I2C
Follow CutshortSubodh Popalwar
Software Engineer, Memorres