System on a chip jobs

4+ System on a chip Jobs in India

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System Hardware

at Rivos Inc

Posted by Deepa Savant

Taiwan

3 - 20 yrs

₹2L - ₹15L / yr

System on a chip

ODM

NPI

I2C

SPI

+6 more

(TAIWAN) HSINCHU, TAIWAN /

ENGINEERING – PLATFORM ENGINEERING (HW) /

FULL-TIME

/ HYBRID

Positions are open for full-time engineers in the platform and board design.

Responsibilities

Schematic capture, board block design, defining routing constraints, layout review, and simulation
System design for chip bring-up boards and final systems
Lab bring-up, test, and debugging
Co-designing with power and signal integrity analysis specialists
High-speed interface characterization
Debugging system-level issues
Resolving system-level issues related to silicon validation and characterization
Work with ODMs to facilitate the NPI (New Product Introduction) process

Requirements

Experience designing SoC/CPU boards (schematic, layout, manufacturing, debug)
Familiarity with a variety of board-level interfaces: I2C, SPI, DDR, etc
Knowledge of high-speed, high-power, system design
Design and analysis of power supplies
CPU/SoC/Microcontroller system architecture familiarity
Test automation expertise using Python or other languages
Board-level analog and digital circuit design expertise
HDL experience is a plus
Excellent skills in problem-solving, written and verbal communication, excellent organization skills, and highly self-motivated.
Ability to work well in a team and be productive under aggressive schedules.
Desire to learn new skills and attack novel problems.
Able to travel to ODM’s factory and/or Rivos’s oversea office for on-site support and meetings

Education and Experience

Master’s Degree or Bachelor’s Degree in the technical subject area.

Note

Annual job salary: The annual job salary mentioned in the posting is a default number taken by cutshort and is inaccurate.

Resumes

Interested folks with 3+ years of experience, Please reach out to the Job Poster to learn more about the job and discuss details.

(TAIWAN) HSINCHU, TAIWAN /

ENGINEERING – PLATFORM ENGINEERING (HW) /

FULL-TIME

/ HYBRID

Positions are open for full-time engineers in the platform and board design.

Responsibilities

Schematic capture, board block design, defining routing constraints, layout review, and simulation
System design for chip bring-up boards and final systems
Lab bring-up, test, and debugging
Co-designing with power and signal integrity analysis specialists
High-speed interface characterization
Debugging system-level issues
Resolving system-level issues related to silicon validation and characterization
Work with ODMs to facilitate the NPI (New Product Introduction) process

Requirements

Experience designing SoC/CPU boards (schematic, layout, manufacturing, debug)
Familiarity with a variety of board-level interfaces: I2C, SPI, DDR, etc
Knowledge of high-speed, high-power, system design
Design and analysis of power supplies
CPU/SoC/Microcontroller system architecture familiarity
Test automation expertise using Python or other languages
Board-level analog and digital circuit design expertise
HDL experience is a plus
Excellent skills in problem-solving, written and verbal communication, excellent organization skills, and highly self-motivated.
Ability to work well in a team and be productive under aggressive schedules.
Desire to learn new skills and attack novel problems.
Able to travel to ODM’s factory and/or Rivos’s oversea office for on-site support and meetings

Education and Experience

Master’s Degree or Bachelor’s Degree in the technical subject area.

Silicon DFT - Full time

at Rivos Inc

Posted by Deepa Savant

Bengaluru (Bangalore)

4 - 18 yrs

₹3L - ₹15L / yr

DFT

System on a chip

Python

CPU

(INDIA) BANGALORE, INDIA /

ENGINEERING – SILICON ENGINEERING /

FULL-TIME

Positions are open for full-time in the areas of DFT design from unit level to chip level, involving all aspects of DFT design functions from scan, MBIST, to ATPG. Roles in the areas of CPU and SOC DFT design and verification.

Responsibilities

Define DFT strategy and methodologies
Design the DFT features
Define test structures, debug structures, and test plans
Create test vectors or oversee their creation
Collaborate with physical design team to close requirements
Validate DFT requirements are being met
Work with designers to increase test coverage, debug observability and flexibility
Verify post-PD designs meet DFT requirements
Work with verification engineers, stepping in to do run tests when needed

Requirements

Good knowledge of digital logic design, microprocessor, debug feature, DFT architecture, CPU architecture, and microarchitecture
Knowledge of DFT and structural debug concepts and methodologies: JTAG, IEEE1500, MBIST, scan dump, memory dump
Knowledge of Verilog and experience with simulators and waveform debugging tools
Knowledge of Verilog / SystemVerilog
Knowledge of Python, , Shell scripting, Makefiles, TCL a plus
Excellent skills in problem solving, written and verbal communication, excellent organization skills, and highly self-motivated.
Ability to work well in a team and be productive under aggressive schedules.

Education and Experience

PhD, Master’s Degree or Bachelor’s Degree in technical subject area.

Note:
Annual job salary: The annual job salary mentioned in this posting is a default number taken by cutshort and is inaccurate. <Not mentioned/ disclosed by Rivos>

Resumes:
Interested folks with 3+ years of experience to 20 years of experience into Silicon DFT, Please reach out to the Recruiter Deepa Savant to learn more about the job and discuss details.

(INDIA) BANGALORE, INDIA /

ENGINEERING – SILICON ENGINEERING /

FULL-TIME

Responsibilities

Define DFT strategy and methodologies
Design the DFT features
Define test structures, debug structures, and test plans
Create test vectors or oversee their creation
Collaborate with physical design team to close requirements
Validate DFT requirements are being met
Work with designers to increase test coverage, debug observability and flexibility
Verify post-PD designs meet DFT requirements
Work with verification engineers, stepping in to do run tests when needed

Requirements

Good knowledge of digital logic design, microprocessor, debug feature, DFT architecture, CPU architecture, and microarchitecture
Knowledge of DFT and structural debug concepts and methodologies: JTAG, IEEE1500, MBIST, scan dump, memory dump
Knowledge of Verilog and experience with simulators and waveform debugging tools
Knowledge of Verilog / SystemVerilog
Knowledge of Python, , Shell scripting, Makefiles, TCL a plus
Excellent skills in problem solving, written and verbal communication, excellent organization skills, and highly self-motivated.
Ability to work well in a team and be productive under aggressive schedules.

Education and Experience

Silicon CPU /SOC Verification - Full-time

at Rivos Inc

Posted by Deepa Savant

Bengaluru (Bangalore)

2 - 20 yrs

₹1L - ₹15L / yr

System on a chip

CPU

SOC

(INDIA) BANGALORE, INDIA /

ENGINEERING – SILICON ENGINEERING /

FULL-TIME

Positions are open for full-time and Co-op/internship in the areas of CPU and SOC verification from unit level to chip level as well as all aspects of verification such as functional, microarchitecture, performance, and formal.

We are looking for all levels of talent, from entrance to advanced level of experience.

Responsibilities

Work closely with architecture and RTL designers on verifying the functionality correctness of the design
Reviewing Architecture and Design Specifications
Develop test plans and test environments
Develop tests in assembly, C/C++, or vectors according to test plans
Develop coverage monitors and analyze coverage to ensure all the test cases in the plans are covered
Develop checkers in SystemVerilog or C-base transactors to verify the design
Write assertions and apply formal verification to the designImplementing test benches, generating directed/constrained random tests
Debugging failures, running simulations, tracking bugs
Handling schedules and supporting multi-functional engineering effortAssisting in verification flows, automation scripts and regressions

Requirements

In-depth knowledge of digital logic design, CPU/SOC architecture and microarchitecture.
Sophisticated knowledge of SystemVerilog.
Experienced level knowledge C/C++.Relevant knowledge of verification methodologies and tools such as simulators, waveform viewers, build and run automation, coverage collection.
Basic knowledge of formal verification methodology is a plus.
Excellent knowledge of one of the scripting languages such as Python, TCL is a plus.
Excellent skills in problem solving, written and verbal communication, excellent organization skills, and highly self-motivated.
Ability to work well in a team and be productive under aggressive schedules.

Education and Experience

PhD, Master’s Degree or Bachelor’s Degree in technical subject area.

Note:
Annual job salary: The annual job salary mentioned in this posting is a default number taken by cutshort and is inaccurate. <Not mentioned/ disclosed by Rivos>

Resumes:
Interested folks with 2+ years to 20 years of experience into Silicon CPU or SOC Verification, Please reach out to the Recruiter Deepa Savant to learn more about the job and discuss details.

(INDIA) BANGALORE, INDIA /

ENGINEERING – SILICON ENGINEERING /

FULL-TIME

We are looking for all levels of talent, from entrance to advanced level of experience.

Responsibilities

Work closely with architecture and RTL designers on verifying the functionality correctness of the design
Reviewing Architecture and Design Specifications
Develop test plans and test environments
Develop tests in assembly, C/C++, or vectors according to test plans
Develop coverage monitors and analyze coverage to ensure all the test cases in the plans are covered
Develop checkers in SystemVerilog or C-base transactors to verify the design
Write assertions and apply formal verification to the designImplementing test benches, generating directed/constrained random tests
Debugging failures, running simulations, tracking bugs
Handling schedules and supporting multi-functional engineering effortAssisting in verification flows, automation scripts and regressions

Requirements

In-depth knowledge of digital logic design, CPU/SOC architecture and microarchitecture.
Sophisticated knowledge of SystemVerilog.
Experienced level knowledge C/C++.Relevant knowledge of verification methodologies and tools such as simulators, waveform viewers, build and run automation, coverage collection.
Basic knowledge of formal verification methodology is a plus.
Excellent knowledge of one of the scripting languages such as Python, TCL is a plus.
Excellent skills in problem solving, written and verbal communication, excellent organization skills, and highly self-motivated.
Ability to work well in a team and be productive under aggressive schedules.

Education and Experience

PhD, Master’s Degree or Bachelor’s Degree in technical subject area.

Principal Embedded Systems Engineer

at Hyerspecai

1 recruiter

Posted by Venkata Kolla

Hyderabad

7 - 15 yrs

$15K - $40K / yr

C++

Embedded software

FPGA

PCB

+3 more

Summary:

Hyperspec is building a real time local map for self-driving cars and using cross view localization to enable ubiquitous autonomy. Hyperspec is a VC funded startup.

The principal embedded systems engineer will have deep expertise in embedded systems design, development and worked for years on embedded systems teams. This person is a leader and mentor to junior engineers and shares knowledge about the design and development of embedded systems.

Responsibilities:

Serves as an expert in all aspects of embedded projects and embedded systems—including designing, developing, testing, and perfecting designs
Responsible for updating and working with executive leadership on the development of embedded systems and status of projects
Provides guidance and mentoring to other members of the team

Requirements:

Minimum of bachelors' degree in computer science or engineering
At least ten years of engineering experience with expertise in software engineering, data structures, and programming techniques
Deep expertise in C/C++ programming
Experience with FPGAs, PCB, Xilinx, Altera, or similar SoCs.
Experience with ISPs, Cameras, Switches a plus.
Experience in working with real-time operating systems, communications protocols and firmware design.

Experience in interfaces, IP protocols, and hardware subsystems.
Experience in working as part of a team and leading teams.

Summary:

Hyperspec is building a real time local map for self-driving cars and using cross view localization to enable ubiquitous autonomy. Hyperspec is a VC funded startup.

Responsibilities:

Serves as an expert in all aspects of embedded projects and embedded systems—including designing, developing, testing, and perfecting designs
Responsible for updating and working with executive leadership on the development of embedded systems and status of projects
Provides guidance and mentoring to other members of the team

Requirements:

Minimum of bachelors' degree in computer science or engineering
At least ten years of engineering experience with expertise in software engineering, data structures, and programming techniques
Deep expertise in C/C++ programming
Experience with FPGAs, PCB, Xilinx, Altera, or similar SoCs.
Experience with ISPs, Cameras, Switches a plus.
Experience in working with real-time operating systems, communications protocols and firmware design.

Experience in interfaces, IP protocols, and hardware subsystems.
Experience in working as part of a team and leading teams.

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