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3+ Tcl Jobs in India

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QFocus AI
Bengaluru (Bangalore)
5 - 10 yrs
₹30L - ₹50L / yr
Synopsys
cadence
Formal verification
assertion
Perl
+5 more


About the organization

QFocus AI Pvt. Ltd. (QFAI), a wholly owned subsidiary of QFocus Technologies LLC, is a consulting-led engineering services company with sharp focus on supporting next gen advanced products development across AI/ML, Compute, Communication, Storage and Consumer Electronics. Our mission is to help our customers deliver cutting-edge products on time ensuring world-class quality.


Why Join QFAI? Join a passionate team, dedicated to making a difference.  

We are a close-knit team, with strong mission, vision and values that guide our day-to-day.  Recognition of work, respect, and our multicultural community are key aspects of the employee experience and contribute to our continued success.  Would you like to be part of our story? Don't hesitate, come and join us! 

 

About this opportunity – Formal Verification Engineer

We are seeking a highly skilled and passionate Formal Verification Engineer to join our team working with the best in the Industry, developing innovative ASIC solutions for data center and AI Infrastructure. The ideal candidate will develop comprehensive formal test plans and be responsible for complete formal verification sign-off of single or multiple complex blocks. The role also provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC Design, Emulation and Post-Silicon teams towards creating a first-pass silicon success.

 

Key Responsibilities:

·      Contribute to Formal Verification applying and evangelizing state of the art Formal Verification Methodologies across IP-level, subsystem-level and SOC Level.

·      Collaborate with Architecture and Design teams to develop formal specifications and implementations.

·      Define formal verification scope, create formal environments, and achieve coverage sign-off using targeted formal verification techniques.

·      Develop comprehensive formal test plans, including unique security requirement verification.

·      Build reusable and scalable formal verification environments and deploy relevant tools.

·      Evaluate and recommend EDA solutions for Formal Verification and drive improvements to methodologies and flows.

·      Debug complex issues in RTL designs based on formal results and contribute to design improvements.

 

Required Skills:

 

  1. Strong hands-on experience with Formal Verification tools (e.g., JasperGold, VC-Formal, Questa Formal).
  2. Experience writing formal properties using System Verilog Assertions (SVA) or Property Specification Language (PSL).
  3. Proven understanding of Formal Verification methodologies, complexity reduction techniques, and abstraction techniques.
  4. Fluency in hardware description languages, such as SystemVerilog.
  5. Proficiency in scripting languages such as Python, Perl, or Tcl within Unix/Linux environments.

 Education:

 

Bachelor's degree in Computer Science, Computer Engineering, Electrical Engineering, or a related technical field, or equivalent practical experience.

 

Experience:

 

5+ years of experience in Design Verification, with at least 1 year in Formal Verification.

 

QFocus AI Pvt Ltd is an Equal Employment Opportunity employer.


 


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India, Taipei (Taiwan ), USA
4 - 18 yrs
₹10L - ₹15L / yr
Circuit Design
SPICE
Simulation
Tcl
Perl
+5 more
Standard Cell Library Automation/ CAD Engineer

Rivos Custom Circuits team is seeking highly motivated candidates for custom backend design automation and standard cell characterization. The role will be at the center of a state-of-the art circuit design effort, interfacing with all disciplines and have a critical impact on getting products to market quickly. The qualified candidate will be responsible for automating tools and methodologies for standard cell characterization
Key qualifications•


The ideal candidate will have 4+ years of experience in backend design automation and standard cell characterization


• Prior experience and proven success of successfully designing high performance standard cells is desired
• Solid knowledge of circuit analysis, reliability, extraction, and SPICE simulation to validate design performance
• Knowledge of industry standard hardware design CAD software and required standard cell design view generation and validation.
• Solid foundation of scripting fluency in TCL, Perl/Python
• Basic knowledge of advanced FinFet device and standard cell circuit and layout
• Ability to work well in a team and be productive under aggressive schedules.
• Excellent problem solving, written and verbal communicationResponsibilities• Responsible for timing and power characterization and generation of standard cell EDA views,
• Other job duties include performing QA including EM/IR and design checks
• adding automation to improve design productivity


Note:
Annual job salary: The annual job salary mentioned in this posting is a default number taken by cutshort and is inaccurate. <Not mentioned/ disclosed by Rivos>

Resumes:
Interested folks with 4+ years of experience in Standard cell, Please reach out to the Recruiter Deepa Savant to learn more about the job and discuss details. 
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Paxterra Solutions

at Paxterra Solutions

1 recruiter
Vaishna M M
Posted by Vaishna M M
Bengaluru (Bangalore)
2 - 5 yrs
₹5L - ₹10L / yr
Regression Testing
Manual testing
skill iconPython
Tcl
Test Automation (QA)
+3 more

Candidate should have experince in L2 L3 Testing
Experience in Automation, Manual and Rgression Testing
Scripting language Python
Experience in Networking

 

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