Design Verification

1. Coding and Debugging in C language.
2. Knowledge on ARM based architectures of 8/16/32 Microcontrollers,UART, ADC, DAC,Ethernet, SPI,CAN,I2C and I2S.
3. FPGA RTL coding and Simulation using Verilog/VHDL

Qualification - BE/B.Tech (ECE), M.Sc.(Electronics)

Only Defense and Aerospace, Electronics, Semi-Conductors,

(No Automative industry)

AVANTEL LIMITED is a technology driven public limited company with focus on developing innovative wireless communication products and solutions to meet unique requirements of defense, railways, and telecom sectors. The organization is certified against AS 9100D and ISO 9001:2015 standards for Quality Management System. For more details visit www.avantel.in.

INNOPHASE is a rapidly growing communications semiconductor startup with headquarters located in San Diego, CA. It is an exciting time to join InnoPhase and work with a brilliant team of engineers to design innovative wireless products and solutions for IoT/5G.

InnoPhase Bangalore is looking for a Senior Design Verification (DV) Engineer to join a growing start up semiconductor development organization and to help drive excellence in our IOT/5G products.

Responsibilities:

• Follow and help define the team's design verification methodology.
• Write bus functional models that drive and monitor stimulus.
• Plans and implements block and integration level scoreboards and checkers to verify functional behavior.
• Experience constructing chip-level System Verilog and UVM test bench environments, writing System Verilog Assertions (SVAs), with embedded software design and test.
• Develop RAL test plan at SOC/IP level and its implementation.
• Write and analyze functional coverage, providing input to block-level milestones.
• Triage regression failures and identify logic bugs, while driving bug closure.
• Debug test cases and report verification results to achieve the expected code/functional coverage goal. Utilize constrained random verification, functional coverage, code coverage and assertions to achieve goals.

Knowledge and Skills Required:

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science or equivalent.
• 5+ years of experience in VLSI design or verification
• Excellent collaboration, teamwork and communication skills
• Significant experience in reviewing and modifying IP block verification plans, a real plus if created such plans in collaboration with design engineering.
• Track record of completing IP block verification to acceptable coverage metrics.
• Excellent debugging skills, with experience debugging RTL in the block and/or chip-level environments.
• Working knowledge of OVM or UVM methodologies.
• Good analytical and problem-solving skills.
• Proficient knowledge of programming and scripting, hardware description language, electronic design automation (EDA), and/or FPGA tools.

About Company

Espressif Systems is a multinational, fabless semiconductor company established in 2008, with headquarters in Shanghai and offices in Greater China, India and Europe. We have a passionate team of engineers and scientists from all over the world, focused on developing cutting-edge WiFi-and-Bluetooth, low-power, IoT solutions. Among our popular products are the ESP8266 and ESP32 series of chips, modules and development boards. Espressif has opened a Technology Center in Pune(Baner), India, which will focus on embedded software engineering and IoT solutions development for our growing customers.

At Espressif, communication, collaboration and innovation are of paramount importance. That's why professionals and engineers from around the world have chosen to further their careers at Espressif Systems. They are passionate and committed to developing innovative products. And they are here to ensure that fast,secure and green IoT technology can be available to all. Come and join Espressif, so that you, too, can partake in Espressif's mission in the IoT industry.

BASIC QUALIFICATIONS

• M.Tech/B. Tech in the field of VLSI/Electronics engineering. 
• Proficiency in UVM/SV and C/C++ based functional verification 
• Experience in UPF based low power design verification
• Automation skills in PERL and/or TCL and/or Shell* 
• Team player, with good problem solving and communication skills. 

JOB DESCRIPTION 

• Drive functional verification at IP/SoC level using UVM/SV test bench
• Work closely with design team to define comprehensive feature test plans
• Perform functional and code coverage for logic verification sign-off
• Must have worked on ARM/RISC-V CPU based designs
• Must have performed gate level sim at SoC level
• Pre and Post-silicon debug/validation experience will be a plus

INTERPERSONAL SKILLS:

• Energetic, self-motivated
• Pro-active, oriented on execution
• Attentive to details and quality
• Team player
• Good communications and reporting skills

• Degree : B.E. or M.S. EE/CS/CE
• Methodologies: SV, UVM & OVM
• Areas of Work: Digital Verification (both IP / SOC)
• Protocol : Knowledge of PCIe/DDR/Ethernet/USB is Plus
• Familiar with Bus protocols like AXI, AHB, SPI and I2C