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We are hiring a Principal Engineer – Physical Design to lead end-to-end implementation of advanced-node SoCs (7nm and below), from RTL to GDSII.

Key Responsibilities:

• Lead SoC / full-chip physical design and integration
• Drive floorplanning, partitioning, and P&R (APR)
• Define chip-level architecture for performance, power, and area
• Own clocking strategy, power planning, and dataflow
• Handle IO ring design, bump planning, and package co-design
• Ensure physical verification closure (DRC, LVS, DFM)
• Develop and own P&R flows and methodologies
• Collaborate with cross-functional teams (architecture, RTL, packaging)
• Mentor junior engineers and lead execution

Requirements:

• 15+ years in VLSI Physical Design
• Experience in 7nm or below technology nodes
• Strong expertise in floorplanning, STA, and P&R
• Hands-on with tools like ICC2 / Innovus / PrimeTime
• Experience in full-chip SoC tape-outs
• Strong understanding of ESD, latch-up, and foundry rules
• Experience with package integration and RDL is a plus