- Experience in designing and implementing verification environments for complex RTL designs
- Well-versed in the use of hardware verification languages e.g. SystemVerilog or Specman e
- Verification methodologies such as UVM
- Understanding of end-to-end verification processes, from test plan creation through to verification closure
- Ability to quickly understand and apply complex specification detail
- Understanding of the fundamentals of computer architecture, with an emphasis on pipelining, exception handling, memory systems
- Practical experience of working on microprocessor designs
- In-depth understanding of memory protection, memory translation, vector processing in CPUs, exception and interrupt handling.
- Understanding of constrained random stimulus, the goals and general usefulness of different types of coverage in hardware, as well as checking methodologies and behavioral functional models.
- Knowledge of assembly language (preferably Arm), and/or C/C++
- In-depth technical reviewing of others work
Shubham Vishwakarma
Full Stack Developer - Averlon
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Full Stack Developer - Averlon