Physical Design Engineers

1.Strong background of ASIC Physical Design: Floor planning, P&R, Extraction, IR Drop Analysis, Static Timing and Signal Integrity.                          
2.Hands-on experience on technology nodes like 7nm, 14nm, 10nm.
3.Good knowledge of EDA tools from Synopsys , Cadence and Mentor              
4.Hands-on experience in floor planning, placement optimizations, CTS and routing.                                  
5.Hands-on experience in cadence or Synopsys tool (Encounter, ICC, PT/PTSI, TEMPUS, DC, RC, VOLTAS)

JOB DESCRIPTION PHYSCIAL DESIGN MANDATORY IMPLEMENTATION SKILLS • Netlist to GDSII at block level, Subsystem Level and at Full chip. • Worked on multiple tapeouts on Netlist to GDSII • Hierarchical partitioning and budgeting of block-level subsystems. • Implementation of high performance (HP) cores, low power designs • Node experience upto 7nm, 10nm, 14nm, 28nm. • Timing Signoff in loop through STA and ECO cycle at block and at interface. • Block level floor planning, power planning and IR drop analysis. • Scan chain reordering / Scan Chain repartitioning • CTS expertise and clock tree constraints creation for meeting specifications • MMMC optimization at Block and Sub-System Level • Timing closure with Crosstalk and AOCV / POCV • TCL scripting to fundamentally understand tool usage. MANDATORY EDA SKILLS • PnR tools such as Synopsys ICC/ICC2 and/or Cadence Innovus and/or Mentor Graphics Olympus/Pinnacle and /or Atoptech Apisa/Apogee OPTIONAL AND GOOD TO HAVE SKILLS • Good knowledge of standard cell libraries - circuit design and cell layout. • Good understanding of STA, EM / IR and sign-off flows • Formal verification at various levels of design implementation • Low Power Design (General Methodology, CPF, UPF, atleast one of them) • PERL Scripting and creating quick procedures for solutions • Full Chip Implementation will be an added advantage • Develop, customize, support and maintain physical design flows and methodologies. OPTIONAL AND EDA SKILLS DC, PT, PT-SI, Tweaker, Calibre, LEC, CLP, Spyglass PD HIRING REQUIREMENT RANGE 3 – 6 years 7 positions Block Level and Sub-System Level Implementations mandatory 7+ years 5 positions Block Level, Sub-System, Top-Level Implementations mandatory LOCATION Bangalore, India About the company : BLR Labs is a well funded startup Founded and managed by Passionate, Senior industry Professionals having more than 100 man years’, serial entrepreneurship experience from, Automotive, Mobility, Telecom, VLSI and Embedded Systems Design Engineering. We are a fast growing team of 50 and expecting to reach to 200 mark by end of the current FY. “BLR Labs aspires to create visionaries and entrepreneurs through co-creation. Great companies are built around great people & BLR Labs to achieve our vision have given highest importance and invested in building strong fundamentals such as 4Es (Express, Empathize, Empower & Enroll) & 4Is (Integrity, Innovation, Integration & Intellect) to nurture & cherish our talent force such as being an equal opportunity employer, skill upgradation to enhance our engineers to Intellect levels, creating a culture office to promote fearless & compassionate attitude through our fun @ work programs etc makes for a great working space. We have plans to establish, Labs, ODCs for various MNCs and to get started with our Overseas operations in the near future.