About Swedium Global Services
Swedium Global is the growing System Engineering and Solution Company, offers services like Engineering R&D Services, Custom Application Development, Web Application Development, Consultancy and Testing Services to clients across the globe for onsite and offshore business model. We provide industry solutions to our customer through our dedicated development center in Bangalore (India) and Stockholm (Sweden). Swedium Global is founded by a talented team of young and enterprising IT professionals and aims at blending knowledge and skills to provide results that match your requirements. This is the place where we believe in listening, analyzing, advising and implementing new projects and concepts to effectively present complex information. We have also worked with some of the most successful and expertise individuals, entrepreneurs and corporations and bringing solutions to their most challenging and complex issues of the day.
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Physical Design - JD
Experience: 2-20 yrs
1.Strong background of ASIC Physical Design: Floor planning, P&R, Extraction, IR Drop Analysis, Static Timing and Signal Integrity.
2.Hands-on experience on technology nodes like 7nm, 14nm, 10nm.
3.Good knowledge of EDA tools from Synopsys , Cadence and Mentor
4.Hands-on experience in floor planning, placement optimizations, CTS and routing.
5.Hands-on experience in cadence or Synopsys tool (Encounter, ICC, PT/PTSI, TEMPUS, DC, RC, VOLTAS)
1.SV, UVM, USB, DDR, PCIE, Ethernet, Axi, MIPI. Any one of the protocols will
be added advantage.
2.Experience in verification of complex IPs or SoCs.
3. Expertise in SoC Verification using C and SV/UVM.Expertise in AMBA
protocols
4. AXI/AHB/APB and experience in working with ARM Processors.
5. Expertise in Test Plan creation and Verification technologies like Code
Coverage, Functional Coverage and Assertions.
Skills/Experience
Experience with complete flows involving timing closure of high speed digital design using scripting languages and design automation.
Has deep knowledge of Xilinx FPGA implementation and tools.
Experience in state of the art tools and flows.
Working knowledge in Verilog and System Verilog.
Job Requirements
Bachelors in Electronics Engineering.
Strong knowledge of ASIC and/or FPGA design methodology and should be well versed in front-end design, simulation, and verification CAD tools.
Relevant FPGA/ASIC engineering design and verification experience is entertained.
Excellent verbal, written and communication skills are required.
Excellent follow-through, motivation, and persistence
Strong technical judgment and decision making abilities.
Knowledge of digital board design and signal integrity principles is a plus.
Dear Connections,
Roles & Responsibility:-
Should execute block level floor planning, PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks.
Physical Design Implementation on advanced technology nodes like 28nm, 20nm for block level implementation. Good understanding on low power concepts. Good understanding on top level physical design, partitioning and timing constraints, IR Drop.
Candidate should be from semiconductor/'ASIC industry
Excellent knowledge on GDS To Netlift