ASIC Design

ASIC Design at LeapFrog Semiconductor · Raheja Chancery, Brigade Road, Bangalore · 5 - 10 years · Raised funding · Posted 5 Sep 2023

ASIC Design

at LeapFrog Semiconductor

Posted by Srinivas Chakravarthy

5 - 10 yrs

Best in industry

Raheja Chancery, Brigade Road, Bangalore

Skills

Responsive Design

Should have been part of multiple tape-outs
Experience on multiple frontend tools flow ( spyglass, synthesis, constraint validation, power analysis, LEC,Coverage analysis)
For DSP / Datapath IP developers
Should have hands-on DSP hardware implementation ( RTL coding, synthesis) experience with good understanding of digital communication concepts, DSP algorithms, fixed point /floating point arithmetic, DSP data path optimizations
Background in FFT/LDPC/ Digital filter design is desirable
Background in baseband hardware design for WLAN/LTE/Bluetooth /Cable Modem/5G technologies is desirable
Background in RTL implementation of SIMD / Vector processing engines
For SoC Developers
Should have owned large SOC / Subsystems integration with in depth domain knowledge of one or multiple areas below
CPU Subsystem components : Memory controllers, Interconnects IPs , Interrupt controllers etc
Integration of complex IPs like PCIE, Ethernet ( MAC and PCS), DDR controller
SOC Power Management

Should have been part of multiple tape-outs
Experience on multiple frontend tools flow ( spyglass, synthesis, constraint validation, power analysis, LEC,Coverage analysis)
For DSP / Datapath IP developers
Should have hands-on DSP hardware implementation ( RTL coding, synthesis) experience with good understanding of digital communication concepts, DSP algorithms, fixed point /floating point arithmetic, DSP data path optimizations
Background in FFT/LDPC/ Digital filter design is desirable
Background in baseband hardware design for WLAN/LTE/Bluetooth /Cable Modem/5G technologies is desirable
Background in RTL implementation of SIMD / Vector processing engines
For SoC Developers
Should have owned large SOC / Subsystems integration with in depth domain knowledge of one or multiple areas below
CPU Subsystem components : Memory controllers, Interconnects IPs , Interrupt controllers etc
Integration of complex IPs like PCIE, Ethernet ( MAC and PCS), DDR controller
SOC Power Management

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