Physical Integration Engineer at Bengaluru tech startup · Remote only · 6 - 11 years · ₹15L - ₹27L / yr · Remote only · Posted 26 Oct 2025
Physical Design Integration Engineer
Bengaluru, Karnataka, India
Role
Join our close-knit physical design team where you'll excel in synthesizing, placing, routing and integrating high speed designs. Experience the full spectrum of physical design and implementation, collaborating closely with the RTL team and integrating these blocks seamlessly into the full-chip architecture.
Minimum Skills & Qualifications
10+ years of physical design, integration & physical verification experience.
Strong knowledge of block level and full-chip physical verification methodology.
Experience with the complete physical design flow.
Skills in Design Compiler, Fusion Compiler, ICC2 or similar physical design tools
Expert with ICV or Calibre tools resolving block and full-chip DRC and LVS issues.
Expert with IR/EM analysis and resolution
Good understanding of full chip floor planning and integration.
Strong experience in full chip timing closure
Demonstrated ability to work with RTL teams to optimize for physical design
Ability to independently debug and resolve physical verification Issues
BS or MS in Electrical Engineering
Preferred Skills:
Knowledge of Synopsys tool suite is a plus.
Good scripting skills with languages like Tcl and Python. Ability to make flow enhancements.
Shubham Vishwakarma
Full Stack Developer - Averlon
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Hello Everyone
ElevarSoC hiring for Bangalore, Hyderabad locations
3-6 years of experience with Good DFT concepts in SCAN INSERTION, ATPG and Simulations.
Good exposure to Synth, ATPG tools (Mentor) : DRC & coverage analysis, Timing/no timing (VCS) simulations.
Anyone already worked for Qcomm/product company is preferable.
Candidate should be independent in handling the given task.
Mandatory Skills:
ATPG trace (DRC), Stuck at and TDF Coverage Analysis
ATPG no timing and timing vector simulations
Apply now!!
Do you want to own the PMIC, PLL, and PCIe buffer architectures that ship in millions of vehicles? Do you want to build and lead the team solving India's toughest automotive power and clocking challenges?
Role: Head of Engineering
Level Five Cartronics | Fabless Automotive Semiconductor Design
Location: MG Road, Bengaluru, Karnataka, India (On-site)
About Us
Founded by serial Entrepreneurs, Level Five Cartronics is a fabless semiconductor design company headquartered in Bengaluru, building automotive-grade Power Management ICs (PMICs), high-precision oscillators, and high-performance phase-locked loops (PLLs) for the next generation of vehicle electronics. Our portfolio centres on low-EMI power delivery — including spread-spectrum EMI suppression — and low-jitter clocking and interface solutions for safety-critical solutions and infotainment systems. We design DC-DC converters, LDOs, and clock distribution networks (including low-jitter PCIe Gen 4, 5, and 6 buffers) in CMOS and BCD high-voltage processes across the 55nm, 90nm and 180nm nodes. We own our products end to end, from architecture through silicon characterization and productization, as part of India's growing fabless semiconductor ecosystem.
The Role
We are looking for a hands-on Head of Engineering, based at our Bengaluru headquarters, to lead our analog/mixed-signal design organization. This is a senior leadership position for an engineer who has personally taken complex automotive power, clocking, and high-speed interface products from concept to high-volume production — and who can build, mentor, and scale the cross-functional team that does it again and again.
You will set the technical direction for our PMIC, oscillator, PLL, and PCIe buffer roadmaps, own design quality and tape-out readiness, and partner closely with characterization, product, and test engineering to ensure every product meets stringent automotive reliability, jitter, and EMC requirements.
What You'll Do
1. Lead and grow the analog/mixed-signal design, layout, and verification teams across multiple product lines, based out of our Bengaluru engineering center.
2. Own the technical architecture and execution of automotive-grade PMICs, DC-DC converters, LDOs, low phase noise Fractional-N phase-locked loops (PLLs), and low-jitter PCIe Gen 4, 5, and 6 buffers.
3. Target high-speed interface applications by driving low phase noise PLL architectures explicitly optimized for PCIe Gen 4, 5, and 6 standards.
4. Drive designs across CMOS and BCD high-voltage processes at 55nm, 90nm and 180nm, from specification through tape-out and qualification.
5. Set and enforce design methodology, review gates, and tape-out criteria; review schematics, layout, and verification plans personally where it matters.
6. Partner with characterization engineers on lab bring-up, silicon debug, and correlation of measured results to simulation.
7. Work side by side with product engineers on productization, test development, yield, and sustaining.
8. Build and lead cross-functional teams; recruit, develop, and retain top analog and layout talent in India's semiconductor talent market.
9. Be a technical authority and final escalation point for difficult design and silicon issues.
What You'll Bring
- Minimum of 12 years (preferably more) of experience in analog/mixed-signal design, layout, and productization.
- Demonstrated track record of taped-out databases and shipping full products in volume, not just isolated blocks.
- Deep expertise across the full flow: schematic design, layout, and lab characterization (understanding how each one constrains the others).
- Hands-on design of DC-DC converters and LDOs in CMOS and BCD high-voltage processes.
- Expertise in clocking and interfaces: deep understanding of low phase noise design, Fractional-N PLL architectures, and low-jitter PCIe Gen 4, 5, and 6 clock buffers/drivers.
- Experience with PMICs, oscillators, and spread-spectrum / EMI suppression techniques.
- Strong working knowledge of the 55nm, 90nm and 180nm process nodes.
- Extensive experience with Cadence EDA tools across the design and verification flow.
- Mixed-signal behavioral modeling in Verilog (Verilog/Verilog-AMS).
- Proven history of working closely with characterization and product engineers through bring-up and ramp.
- Demonstrated success building, leading, and recruiting cross-functional engineering teams.
Nice to Have
- Automotive qualification experience (AEC-Q100, ISO 26262 / functional safety awareness).
- Strong EMC/EMI design and measurement background.
- Experience scaling an engineering organization in a fabless environment, ideally within India's semiconductor ecosystem.
Why Level Five Cartronics
You'll own real products in a fast-moving automotive market, work across the full design-to-silicon flow, and shape the engineering culture of a growing fabless company based in Bengaluru — one of India's leading semiconductor design hubs. If you've built power, clocking, and high-speed interface products that ship in cars and you want to lead the team that builds the next ones, we'd like to talk.
Level Five Cartronics is an equal opportunity employer.
Role: FPGA Design & Validation Engineer
Location: Kokapet, Hyderabad
Work Mode: Work from Office – 5 days/week
Key Requirements
- 5+ years of relevant experience in FPGA Design and Validation
- Hands-on experience validating FPGA designs on physical boards
- Experience with board-level debugging and hardware bring-up
- Hands-on experience using Oscilloscopes for hardware/debugging activities
- Experience with TCL scripting
- Good understanding of Lint and CDC (Clock Domain Crossing)
- Experience with Spirent or other traffic generator tools is an added advantage
- Knowledge of AI Agents and Prompt Engineering is a plus
The ideal candidate would have a combination of FPGA design, board-level validation, hardware debugging and lab testing experience.
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Full Stack Developer - Averlon