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3+ DFT Jobs in India

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Rivos Inc
Deepa Savant
Posted by Deepa Savant
Bengaluru (Bangalore)
4 - 18 yrs
₹3L - ₹15L / yr
DFT
System on a chip
Python
CPU
(INDIA) BANGALORE, INDIA /
ENGINEERING – SILICON ENGINEERING /
FULL-TIME
 
Positions are open for full-time in the areas of DFT design from unit level to chip level, involving all aspects of DFT design functions from scan, MBIST, to ATPG. Roles in the areas of CPU and SOC DFT design and verification.

Responsibilities

    • Define DFT strategy and methodologies
    • Design the DFT features
    • Define test structures, debug structures, and test plans
    • Create test vectors or oversee their creation
    • Collaborate with physical design team to close requirements
    • Validate DFT requirements are being met
    • Work with designers to increase test coverage, debug observability and flexibility
    • Verify post-PD designs meet DFT requirements
    • Work with verification engineers, stepping in to do run tests when needed

Requirements

    • Good knowledge of digital logic design, microprocessor, debug feature, DFT architecture, CPU architecture, and microarchitecture
    • Knowledge of DFT and structural debug concepts and methodologies: JTAG, IEEE1500, MBIST, scan dump, memory dump
    • Knowledge of Verilog and experience with simulators and waveform debugging tools
    • Knowledge of Verilog / SystemVerilog
    • Knowledge of Python, , Shell scripting, Makefiles, TCL a plus
    • Excellent skills in problem solving, written and verbal communication, excellent organization skills, and highly self-motivated.
    • Ability to work well in a team and be productive under aggressive schedules.
Education and Experience
PhD, Master’s Degree or Bachelor’s Degree in technical subject area.


Note:
Annual job salary: The annual job salary mentioned in this posting is a default number taken by cutshort and is inaccurate. <Not mentioned/ disclosed by Rivos>

Resumes:
Interested folks with 3+ years of experience to 20 years of experience into Silicon DFT,  Please reach out to the Recruiter Deepa Savant to learn more about the job and discuss details. 
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Sanguine Global

at Sanguine Global

11 recruiters
Sonika Arora
Posted by Sonika Arora
Bengaluru (Bangalore)
2 - 10 yrs
₹10L - ₹20L / yr
DFT
JTAG
MBIST
ATPG

Job Specification

  1. Experience in JTAG, MBIST , Scan Compression, ATPG, Fault Simulation.
  2. Experience with industry ATPG tools Synopsys Tetra MAX, Cadence Encounter Test or
  3. Mentor Fast Scan ATPG tools Synopsys DFT scan insertion.
  4. Experience with industry simulation tools such as VCS, ModelSim, NC Verilog etc.
  5. Pattern Simulation with and without timing annotation &amp; debugging
 
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Bengaluru (Bangalore)
3 - 4 yrs
₹6L - ₹8L / yr
Altium Designer
DFM
DFT
PCB Design
PCB
+5 more
  • Min. 3-4 years HANDS-ON EXPERIENCE below is mandatory. Altium Designer/Allegro (Preferred tools) Design of multilayer impedance-controlled PCBs
  • Schematic symbol and Footprint Library Creation as per IPC standard.
  • Hands-on experience with high speed and mixed-signal multilayer layout design.
  • Component Placement and Routing plan preparation for design effectiveness
  • Complex layout design with DFM and DFT Considerations.
  • Gerber Generation and CAM Validation

Required Skill Sets:

  • Knowledge of DFM & DFT
  • Knowledge of layer stack-up build.
  • Knowledge of EMI/EMC considerations for the successful layout design.
  • Knowledge of IPC standards.
  • In-depth knowledge of PCB fabrication process and Assembly.
  • Knowledge in deciphering 2D/3D CAD DRAWINGS
  • Willingness to learn new tools, technologies, and processes.

Qualification:

  • Diploma/BE/B. Tech in Electronics or any other discipline.
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